SLLSFQ3 January 2023 MCT8329A
PRODUCTION DATA
In standby mode the gate driver, AVDD LDO and I2C bus are active. The device can be configured to enter standby mode by configuring DEV_MODE to 0b. The entry and exit from standby state is described in #GUID-754FF7A5-463B-4572-BF89-CBC47C9D594C/SLVSCP26607. The standby entry and exit criteria for different input modes (analog or PWM or frequency of I2C) can be derived using Equation 12 through Equation 19.
SPEED COMMAND MODE | ENTER STANDBY CONDITION, DEV_MODE = 0b | EXIT FROM STANDBY CONDITION | ENTER SLEEP CONDITION, DEV_MODE = 1b | EXIT FROM SLEEP CONDITION |
---|---|---|---|---|
Analog input at SPEED/WAKE pin | SPEED/WAKE pin voltage < VEN_SB) | SPEED/WAKE pin voltage > VEX_SB) for tDET_ANA | SPEED/WAKE pin voltage < VEN_SL;
for tDET_SL_ANA (SPD_CTRL_MODE = 00b or 01b) orfor tDET_SL_PWM (SPD_CTRL_MODE = 10b or 11b). |
SPEED/WAKE pin high (V > VIH for tDET_ANA |
Analog input at DACOUT/SOx/SPEED_ANA pin | DACOUT/SOx/SPEED_ANA pin voltage <
VEN_SB or SPEED/WAKE pin low (V < VIL) for tEN_SB_PWM |
DACOUT/SOx/SPEED_ANA pin voltage >
VEX_SB for tDET_ANA
and SPEED/WAKE pin high (V > VIH) for tDET_PWM |
SPEED/WAKE pin low (V < VIL) for tDET_SL_PWM | SPEED/WAKE pin high (V > VIH) for tDET_PWM |
PWM | SPEED/WAKE pin PWM Duty < DUTYEN_SB | SPEED/WAKE pin PWM Duty > DUTYEX_SB | SPEED/WAKE pin low (V < VIL) for tDET_SL_PWM | SPEED/WAKE pin high (V > VIH) for tDET_PWM |
Frequency | SPEED/WAKE pin frequency < FEN_SB | SPEED/WAKE pin frequency > FEX_SB | SPEED/WAKE pin low (V < VIL) for tDET_SL_PWM | SPEED/WAKE pin high (V > VIH) for tDET_PWM |
I2C | SPEED_CTRL < SPEED_CTRLEN_SB | SPEED_CTRL > SPEED_CTRLEX_SB | SPEED/WAKE pin voltage < VIL for
tDET_SL_PWM and SPEED_CTRL is programmed as 0. |
SPEED/WAKE pin voltage > VIH for tDET_PWM |