6.5 Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.
Legend
|
|
|
rw |
Bit can be read and written. |
|
rw-0, rw-1 |
Bit can be read and written. It is reset or set by PUC. |
|
rw-(0), rw-(1) |
Bit can be read and written. It is reset or set by POR. |
|
|
SFR bit is not present in device. |
Figure 6-2 Interrupt Enable Register 1 (Address 00h)
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
UTXIE0 |
URXIE0 |
ACCVIE |
NMIIE |
|
|
OFIE |
WDTIE |
rw-0 |
rw-0 |
rw-0 |
rw-0 |
|
|
rw-0 |
rw-0 |
|
Table 6-4 Interrupt Enable Register 1 Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
UTXIE0 |
RW |
0h |
USART0: UART and SPI transmit interrupt enable |
6 |
URXIE0 |
RW |
0h |
USART0: UART and SPI receive interrupt enable |
5 |
ACCVIE |
RW |
0h |
Flash access violation interrupt enable |
4 |
NMIIE |
RW |
0h |
(Non)maskable interrupt enable |
3-2 |
Unused |
|
|
|
1 |
OFIE |
RW |
0h |
Oscillator fault interrupt enable |
0 |
WDTIE |
RW |
0h |
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. |
Figure 6-3 Interrupt Enable Register 2 (Address 01h)
Figure 6-4 Interrupt Flag Register 1 (Address 02h)
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
UTXIFG0 |
URXIFG0 |
|
NMIIFG |
RSTIFG |
PORIFG |
OFIFG |
WDTIFG |
rw-1 |
rw-0 |
|
rw-0 |
rw-(0) |
rw-(1) |
rw-1 |
rw-(0) |
|
Table 6-5 Interrupt Flag Register 1 Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
UTXIFG0 |
RW |
1h |
USART0: UART and SPI transmit interrupt flag |
6 |
URXIFG0 |
RW |
0h |
USART0: UART and SPI receive interrupt flag |
5 |
Unused |
|
|
|
4 |
NMIIFG |
RW |
0h |
Set by RST/NMI pin |
3 |
RSTIFG |
RW |
0h |
Power-on reset interrupt flag. Set on VCC power up. |
2 |
PORIFG |
RW |
1h |
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up. |
1 |
OFIFG |
RW |
1h |
Flag set on oscillator fault |
0 |
WDTIFG |
RW |
0h |
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. |
Figure 6-5 Interrupt Flag Register 2 (Address 03h)
Figure 6-6 Module Enable Register 1 (Address 04h)
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
UTXE0 |
URXE0
USPIE0 |
|
|
|
|
|
|
rw-0 |
rw-0 |
|
|
|
|
|
|
|
Table 6-6 Module Enable Register 1 Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
UTXE0 |
RW |
0h |
USART0: UART mode transmit enable |
6 |
URXE0
USPIE0 |
RW |
0h |
USART0: UART mode receive enable
USART0: SPI mode transmit and receive enable |
5-0 |
Unused |
|
|
|
Figure 6-7 Module Enable Register 2 (Address 05h)