SLAS701B November   2010  – June 2018 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Terminal Functions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Resistance Characteristics for PW-24 Package
    5. 5.5  Active Mode Supply Current (Into DVCC and AVCC) Excluding External Current
    6. 5.6  Typical Characteristics – Active-Mode Supply Current (Into DVCC and AVCC)
    7. 5.7  Low-Power-Mode Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Typical Characteristics – LPM4 Current
    9. 5.9  Schmitt-Trigger Inputs (Ports Px and RST/NMI)
    10. 5.10 Leakage Current (Ports Px)
    11. 5.11 Outputs (Ports Px)
    12. 5.12 Output Frequency (Ports Px)
    13. 5.13 Typical Characteristics – Outputs
    14. 5.14 POR, BOR
    15. 5.15 Typical Characteristics – POR, BOR
    16. 5.16 Supply Voltage Supervisor (SVS), Supply Voltage Monitor (SVM)
    17. 5.17 Main DCO Characteristics
    18. 5.18 DCO Frequency
    19. 5.19 Calibrated DCO Frequencies – Tolerance
    20. 5.20 Wake-up Times From Lower-Power Modes (LPM3, LPM4)
    21. 5.21 Typical Characteristics – DCO Clock Wake-up Time
    22. 5.22 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    23. 5.23 Crystal Oscillator (XT2)
    24. 5.24 Typical Characteristics – XT2 Oscillator
    25. 5.25 SD24_A, Power Supply
    26. 5.26 SD24_A, Input Range
    27. 5.27 SD24_A, Performance
    28. 5.28 SD24_A, Temperature Sensor and Built-In VCC Sense
    29. 5.29 SD24_A, Built-In Voltage Reference
    30. 5.30 SD24_A, Reference Output Buffer
    31. 5.31 SD24_A, External Reference Input
    32. 5.32 USART0
    33. 5.33 Timer_A3
    34. 5.34 Flash Memory
    35. 5.35 RAM
    36. 5.36 JTAG and Spy-Bi-Wire Interface
    37. 5.37 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers
      1. Table 6-4 Interrupt Enable Register 1 Field Descriptions
      2. Table 6-5 Interrupt Flag Register 1 Field Descriptions
      3. Table 6-6 Module Enable Register 1 Field Descriptions
    6. 6.6  Memory Organization
    7. 6.7  Flash Memory
    8. 6.8  Peripherals
    9. 6.9  Oscillator and System Clock
    10. 6.10 Brownout, Supply Voltage Supervisor
    11. 6.11 Digital I/O
    12. 6.12 Watchdog Timer (WDT+)
    13. 6.13 Timer_A3
    14. 6.14 USART0
    15. 6.15 Hardware Multiplier
    16. 6.16 SD24_A
    17. 6.17 Peripheral File Map
    18. 6.18 I/O Port Schematics
      1. 6.18.1 Port P1 Pin Schematic: P1.0 Input/Output With Schmitt Trigger
      2. 6.18.2 Port P1 Pin Schematic: P1.1 and P1.2 Input/Output With Schmitt Trigger
      3. 6.18.3 Port P1 Pin Schematic: P1.3 Input/Output With Schmitt Trigger
      4. 6.18.4 Port P1 Pin Schematic: P1.4 Input/Output With Schmitt Trigger
      5. 6.18.5 Port P1 Pin Schematic: P1.5 to P1.7 Input/Output With Schmitt Trigger
      6. 6.18.6 Port P2 Pin Schematic: P2.0 Input/Output With Schmitt Trigger
      7. 6.18.7 Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger
      8. 6.18.8 Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger
      9. 6.18.9 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Getting Started
    2. 7.2 Device Nomenclature
    3. 7.3 Tools and Software
    4. 7.4 Documentation Support
    5. 7.5 Related Links
    6. 7.6 Community Resources
    7. 7.7 Trademarks
    8. 7.8 Electrostatic Discharge Caution
    9. 7.9 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants.

Table 4-1 Terminal Functions

TERMINAL I/O DESCRIPTION
NAME NO.
A0.0+ 1 I SD24_A positive analog input A0.0(1)
A0.0- 2 I SD24_A negative analog input A0.0(1)
A1.0+ 3 I SD24_A positive analog input A1.0 (not available on MSP430AFE2x1)(1)
A1.0- 4 I SD24_A negative analog input A1.0 (not available on MSP430AFE2x1)(1)
AVCC 5 Analog supply voltage, positive terminal. Must not power up prior to DVCC.
AVSS 6 Analog supply voltage, negative terminal
VREF 7 I/O Input for an external reference voltage
output for internal reference voltage (can be used as mid-voltage)
A2.0+ 8 I SD24_A positive analog input A2.0 (not available on MSP430AFE2x2 and MSP430AFE2x1)(1)
A2.0- 9 I SD24_A negative analog input A2.0 (not available on MSP430AFE2x2 and MSP430AFE2x1)(1)
TEST/SBWTCK 10 I Selects test mode for JTAG pins on P1.5 to P1.7 and P2.0.
The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input for device programming and test.
RST/NMI/SBWTDIO 11 I Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output for device programming and test.
P1.0/SVSIN/TACLK/SMCLK/TA2 12 I/O General-purpose digital I/O pin
Analog input to supply voltage supervisor
Timer_A3, clock signal TACLK input
SMCLK signal output
Timer_A3, compare: Out2 Output
DVSS 13 Digital supply voltage, negative terminal
P2.6/XT2IN 14 I/O Input terminal of crystal oscillator
General-purpose digital I/O pin
P2.7/XT2OUT 15 I/O Output terminal of crystal oscillator
General-purpose digital I/O pin
DVCC 16 Digital supply voltage, positive terminal.
P1.1/TA1/SDCLK 17 I/O General-purpose digital I/O pin
Timer_A3, capture: CCI1A and CCI1B inputs, compare: Out1 output
SD24_A bit stream clock output
P1.2/TA0/SD0DO 18 I/O General-purpose digital I/O pin
Timer_A3, capture: CCI0A and CCI0B inputs, compare: Out0 output
SD24_A bit stream data output for channel 0
P1.3/UTXD0/SD1DO 19 I/O General-purpose digital I/O pin
Transmit data out - USART0 in UART mode
SD24_A bit stream data output for channel 1 (not available on MSP430AFE2x1)
P1.4/URXD0/SD2DO 20 I/O General-purpose digital I/O pin
Receive data in - USART0 in UART mode
SD24_A bit stream data output for channel 2 (not available on MSP430AFE2x2 and MSP430AFE2x1)
P1.5/SIMO0/SVSOUT/TMS 21 I/O General-purpose digital I/O
Slave in/master out of USART0 in SPI mode
SVS: output of SVS comparator
JTAG test mode select. TMS is used as an input port for device programming and test.
P1.6/SOMI0/TA2/TCK 22 I/O General-purpose digital I/O pin
Slave out/master in of USART0 in SPI mode
Timer_A3, compare: Out2 output
JTAG test clock. TCK is the clock input port for device programming and test.
P1.7/UCLK0/TA1/TDO/TDI 23 I/O General-purpose digital I/O pin
External clock input - USART0 in UART or SPI mode, clock output - USART0/SPI mode.
Timer_A3, compare: Out1 output
JTAG test data output port. TDO/TDI data output or programming data input terminal.
P2.0/STE0/TA0/TDI/TCLK 24 I/O General-purpose digital I/O pin
Slave transmit enable - USART0 in SPI mode.
Timer_A3, compare: Out0 output
JTAG test data input or test clock input for device programming and test.
(1) TI recommends shorting unused analog input pairs and connecting them to analog ground.