6.7.2 Special Function Registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.
Figure 6-4 Interrupt Enable 1 Bit Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
UTXIE0 |
URXIE0 |
ACCVIE |
NMIIE |
Reserved |
OFIE |
WDTIE |
R/W-0 |
R/W-0 |
R/W-0 |
R/W-0 |
R-0 |
R/W-0 |
R/W-0 |
Table 6-6 Interrupt Enable 1 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
UTXIE0 |
R/W |
0 |
USART0: UART and SPI transmit interrupt enable |
6 |
URXIE0 |
R/W |
0 |
USART0: UART and SPI receive interrupt enable |
5 |
ACCVIE |
R/W |
0 |
Flash access violation interrupt enable |
4 |
NMIIE |
R/W |
0 |
Nonmaskable interrupt enable |
3-2 |
Reserved |
R |
0 |
|
1 |
OFIE |
R/W |
0 |
Oscillator-fault interrupt enable |
0 |
WDTIE |
R/W |
0 |
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. |
Figure 6-5 Interrupt Enable 2 Bit Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Reserved |
UTXIE1 |
URXIE1 |
Reserved |
R-0 |
R/W-0 |
R/W-0 |
R-0 |
Table 6-7 Interrupt Enable 2 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-6 |
Reserved |
R |
0 |
|
5 |
UTXIE1 |
R/W |
0 |
USART1: UART and SPI receive interrupt enable |
4 |
URXIE1 |
R/W |
0 |
USART1: UART and SPI transmit interrupt enable |
3-0 |
Reserved |
R/W |
0 |
|
Figure 6-6 Interrupt Flag 1 Bit Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
UTXIFG0 |
URXIFG0 |
Reserved |
NMIIFG |
Reserved |
OFIFG |
WDTIFG |
R/W-1 |
R/W-0 |
R-0 |
R/W-0 |
R-0 |
R/W-1 |
R/W-(0) |
Table 6-8 Interrupt Flag 1 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
UTXIFG0 |
R/W |
1 |
USART0: UART and SPI transmit flag |
6 |
URXIFG0 |
R/W |
0 |
USART0: UART and SPI receive flag |
5 |
Reserved |
R |
0 |
|
4 |
NMIIFG |
R/W |
0 |
Set by RST/NMI pin |
3-2 |
Reserved |
R |
0 |
|
1 |
OFIFG |
R/W |
1 |
Flag set on oscillator fault |
0 |
WDTIFG |
R/W |
(0) |
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power up or a reset condition at the RST/NMI pin in reset mode. |
Figure 6-7 Interrupt Flag 2 Bit Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Reserved |
UTXIFG1 |
URXIFG1 |
Reserved |
R-0 |
R/W-1 |
R/W-0 |
R-0 |
Table 6-9 Interrupt Flag 2 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-6 |
Reserved |
R |
0 |
|
5 |
UTXIFG1 |
R/W |
1 |
USART1: UART and SPI transmit flag |
4 |
URXIFG1 |
R/W |
0 |
USART1: UART and SPI receive flag |
3-0 |
Reserved |
R |
0 |
|
Figure 6-8 Module Enable 1 Bit Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
UTXE0 |
URXE0
USPIE0 |
Reserved |
R/W-0 |
R/W-0 |
R-0 |
Table 6-10 Module Enable 1 Bit Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
UTXE0 |
R/W |
0 |
USART0: UART transmit enable |
6 |
URXE0
USPIE0 |
R/W |
0 |
USART0: UART receive enable
USART0: SPI (synchronous peripheral interface) transmit and receive enable |
5-0 |
Reserved |
R |
0 |
|
Figure 6-9 Module Enable 2 Bit Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Reserved |
UTXE1 |
URXE1
USPIE1 |
Reserved |
R-0 |
R/W-0 |
R/W-0 |
R-0 |
Table 6-11 Module Enable 2 Bit Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-6 |
Reserved |
R |
0 |
|
5 |
|
R/W |
0 |
USART1: UART transmit enable |
4 |
URXE1
USPIE1 |
R/W |
0 |
USART1: UART receive enable
USART1: SPI (synchronous peripheral interface) transmit and receive enable |
3-0 |
Reserved |
R |
0 |
|