SLAS541M June   2007  – March 2022 MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Typical Characteristics – Active Mode Supply Current (Into VCC)
    6. 8.6  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 8.7  Typical Characteristics – LPM4 Current
    8. 8.8  Schmitt-Trigger Inputs (Ports P1 to P8, RST/NMI, JTAG, XIN, and XT2IN)
    9. 8.9  Inputs (Ports P1 and P2)
    10. 8.10 Leakage Current (Ports P1 to P8)
    11. 8.11 Standard Inputs ( RST/NMI)
    12. 8.12 Outputs (Ports P1 to P8)
    13. 8.13 Output Frequency (Ports P1 to P8)
    14. 8.14 Typical Characteristics – Outputs
    15. 8.15 POR and Brownout Reset (BOR)
    16. 8.16 Typical Characteristics – POR and BOR
    17. 8.17 Supply Voltage Supervisor (SVS), Supply Voltage Monitor (SVM)
    18. 8.18 Main DCO Characteristics
    19. 8.19 DCO Frequency
    20. 8.20 Calibrated DCO Frequencies – Tolerance at Calibration
    21. 8.21 Calibrated DCO Frequencies – Tolerance Over Temperature 0°C to 85°C
    22. 8.22 Calibrated DCO Frequencies – Tolerance Over Supply Voltage VCC
    23. 8.23 Calibrated DCO Frequencies – Overall Tolerance
    24. 8.24 Typical Characteristics – Calibrated DCO Frequency
    25. 8.25 Wake-up Times From Lower-Power Modes (LPM3, LPM4)
    26. 8.26 Typical Characteristics – DCO Clock Wake-up Time From LPM3 or LPM4
    27. 8.27 DCO With External Resistor ROSC
    28. 8.28 Typical Characteristics – DCO With External Resistor ROSC
    29. 8.29 Crystal Oscillator LFXT1, Low-Frequency Mode
    30. 8.30 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    31. 8.31 Crystal Oscillator LFXT1, High-Frequency Mode
    32. 8.32 Typical Characteristics – LFXT1 Oscillator in HF Mode (XTS = 1)
    33. 8.33 Crystal Oscillator XT2
    34. 8.34 Typical Characteristics – XT2 Oscillator
    35. 8.35 Timer_A
    36. 8.36 Timer_B
    37. 8.37 USCI (UART Mode)
    38. 8.38 USCI (SPI Master Mode)
    39. 8.39 USCI (SPI Slave Mode)
    40. 8.40 USCI (I2C Mode)
    41. 8.41 Comparator_A+
    42. 8.42 Typical Characteristics – Comparator_A+
    43. 8.43 12-Bit ADC Power Supply and Input Range Conditions
    44. 8.44 12-Bit ADC External Reference
    45. 8.45 12-Bit ADC Built-In Reference
    46. 8.46 12-Bit ADC Timing Parameters
    47. 8.47 12-Bit ADC Linearity Parameters
    48. 8.48 12-Bit ADC Temperature Sensor and Built-In VMID
    49. 8.49 12-Bit DAC Supply Specifications
    50. 8.50 12-Bit DAC Linearity Specifications
    51. 8.51 Typical Characteristics, 12-Bit DAC Linearity Specifications
    52. 8.52 12-Bit DAC Output Specifications
    53. 8.53 12-Bit DAC Reference Input Specifications
    54. 8.54 12-Bit DAC Dynamic Specifications
    55. 8.55 Flash Memory
    56. 8.56 RAM
    57. 8.57 JTAG Interface
    58. 8.58 JTAG Fuse
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Instruction Set
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Special Function Registers (SFRs)
    6. 9.6  Memory Organization
    7. 9.7  Bootloader (BSL)
    8. 9.8  Flash Memory
    9. 9.9  Peripherals
      1. 9.9.1  DMA Controller (MSP430F261x Only)
      2. 9.9.2  Oscillator and System Clock
      3. 9.9.3  Calibration Data Stored in Information Memory Segment A
      4. 9.9.4  Brownout, Supply Voltage Supervisor (SVS)
      5. 9.9.5  Digital I/O
      6. 9.9.6  Watchdog Timer (WDT+)
      7. 9.9.7  Hardware Multiplier
      8. 9.9.8  Universal Serial Communication Interface (USCI)
      9. 9.9.9  Timer_A3
      10. 9.9.10 Timer_B7
      11. 9.9.11 Comparator_A+
      12. 9.9.12 ADC12
      13. 9.9.13 DAC12 (MSP430F261x Only)
      14. 9.9.14 Peripheral File Map
    10. 9.10 Port Diagrams
      1. 9.10.1  Port P1 (P1.0 to P1.7), Input/Output With Schmitt Trigger
      2. 9.10.2  Port P2 (P2.0 to P2.4, P2.6, and P2.7), Input/Output With Schmitt Trigger
      3. 9.10.3  Port P2 (P2.5), Input/Output With Schmitt Trigger
      4. 9.10.4  Port P3 (P3.0 to P3.7), Input/Output With Schmitt Trigger
      5. 9.10.5  Port P4 (P4.0 to P4.7), Input/Output With Schmitt Trigger
      6. 9.10.6  Port P5 (P5.0 to P5.7), Input/Output With Schmitt Trigger
      7. 9.10.7  Port P6 (P6.0 to P6.4), Input/Output With Schmitt Trigger
      8. 9.10.8  Port P6 (P6.5 and P6.6), Input/Output With Schmitt Trigger
      9. 9.10.9  Port P6 (P6.7), Input/Output With Schmitt Trigger
      10. 9.10.10 Port P7 (P7.0 to P7.7), Input/Output With Schmitt Trigger
      11. 9.10.11 Port P8 (P8.0 to P8.5), Input/Output With Schmitt Trigger
      12. 9.10.12 Port P8 (P8.6), Input/Output With Schmitt Trigger
      13. 9.10.13 Port P8 (P8.7), Input/Output With Schmitt Trigger
      14. 9.10.14 JTAG Pins (TMS, TCK, TDI/TCLK, TDO/TDI) Input/Output With Schmitt Trigger
      15. 9.10.15 JTAG Fuse Check Mode
  10. 10Device and Documentation Support
    1. 10.1 Getting Started
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4 Interrupt Vector Addresses

The interrupt vectors and the power up starting address are in the address range of 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the CPU enters LPM4 immediately after power up.

Table 9-3 Interrupt Sources
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power up
External reset
Watchdog Timer+
Flash key violation
PC out of range(1)		 PORIFG
RSTIFG
WDTIFG
KEYV
See (2)		 Reset 0FFFEh 31, highest
NMI
Oscillator fault
Flash memory access violation		 NMIIFG
OFIFG
ACCVIFG(2)(6)		 (Non)maskable,
(Non)maskable,
(Non)maskable		 0FFFCh 30
Timer_B7 TBCCR0 CCIFG(3) Maskable 0FFFAh 29
Timer_B7 TBCCR1 to TBCCR6 CCIFGs, TBIFG(2)(3) Maskable 0FFF8h 28
Comparator_A+ CAIFG Maskable 0FFF6h 27
Watchdog Timer+ WDTIFG Maskable 0FFF4h 26
Timer_A3 TACCR0 CCIFG(3) Maskable 0FFF2h 25
Timer_A3 TACCR1 CCIFG
TACCR2 CCIFG(2)(3)		 Maskable 0FFF0h 24
USCI_A0 or USCI_B0 receive
USCI_B0 I2C status		 UCA0RXIFG, UCB0RXIFG(2)(4) Maskable 0FFEEh 23
USCI_A0 or USCI_B0 transmit
USCI_B0 I2C receive or transmit		 UCA0TXIFG, UCB0TXIFG(2)(5) Maskable 0FFECh 22
ADC12 ADC12IFG(2)(3) Maskable 0FFEAh 21
0FFE8h 20
I/O port P2 (eight flags) P2IFG.0 to P2IFG.7(2)(3) Maskable 0FFE6h 19
I/O port P1 (eight flags) P1IFG.0 to P1IFG.7(2)(3) Maskable 0FFE4h 18
USCI_A1 or USCI_B1 receive
USCI_B1 I2C status		 UCA1RXIFG, UCB1RXIFG(2)(4) Maskable 0FFE2h 17
USCI_A1 or USCI_B1 transmit
USCI_B1 I2C receive or transmit		 UCA1TXIFG, UCB1TXIFG(2)(5) Maskable 0FFE0h 16
DMA DMA0IFG, DMA1IFG, DMA2IFG(2)(3) Maskable 0FFDEh 15
DAC12 DAC12_0IFG, DAC12_1IFG(2)(3) Maskable 0FFDCh 14
See (7)(8) 0FFDAh to 0FFC0h 15 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from within unused address ranges.
(2) Multiple source flags
(3) Interrupt flags are in the module.
(4) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
(5) In UART or SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
(6) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(7) The address 0FFBEh is used as bootloader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password is supplied.
(8) The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if necessary.