5.1 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

5.2 Instruction Set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 5-1 shows examples of the three types of instruction formats; the address modes are listed in Table 5-2.

5.3 Operating Modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

• Active mode ( AM)
  • All clocks are active.
• Low-power mode 0 (LPM0)
  • CPU is disabled.
  • ACLK and SMCLK remain active. MCLK is disabled.
• Low-power mode 1 (LPM1)
  • CPU is disabled.
  • ACLK and SMCLK remain active. MCLK is disabled.
  • DCO’s DC generator is disabled if DCO not used in active mode.
• Low-power mode 2 (LPM2)
  • CPU is disabled.
  • MCLK and SMCLK are disabled.
  • DCO's dc-generator remains enabled.
  • ACLK remains active
• Low-power mode 3 (LPM3)
  • CPU is disabled.
  • MCLK and SMCLK are disabled.
  • DCO's dc-generator is disabled.
  • ACLK remains active.
• Low-power mode 4 (LPM4)
  • CPU is disabled.
  • ACLK is disabled.
  • MCLK and SMCLK are disabled.
  • DCO's dc-generator is disabled.
  • Crystal oscillator is stopped.

5.4 Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFF–0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the CPU goes into LPM4 immediately after power up.

5.5 Special Function Registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

5.5.2 Interrupt Flag Register 1 and 2

Address

7

6

5

4

3

2

1

0

02h

NMIIFG

RSTIFG

PORIFG

OFIFG

WDTIFG

rw-0

rw-(0)

rw-(1)

rw-1

rw-(0)

WDTIFG:	Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG:	Flag set on oscillator fault7
RSTIFG:	External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
PORIFG:	Power-On Reset interrupt flag. Set on VCC power up.
NMIIFG:	Set via RST/NMI-pin

Address

7

6

5

4

3

2

1

0

03h

UCB0 TXIFG

UCB0 RXIFG

UCA0 TXIFG

UCA0 RXIFG

rw-1

rw-0

rw-1

rw-0

UCA0RXIFG	USCI_A0 receive-interrupt flag
UCA0TXIFG	USCI_A0 transmit-interrupt flag
UCB0RXIFG	USCI_B0 receive-interrupt flag
UCB0TXIFG	USCI_B0 transmit-interrupt flag

xxx

Legend:
	rw:	Bit can be read and written.
	rw-0, 1:	Bit can be read and written. It is Reset or Set by PUC.
	rw-(0), (1):	Bit can be read and written. It is Reset or Set by POR.
		SFR bit is not present in device.

5.6 Memory Organization

5.7 Bootstrap Loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see Features of the MSP430 Bootstrap Loader (SLAA089).

5.8 Flash Memory

The flash memory can be programmed via the JTAG port, the bootstrap loader or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0–n.
  Segments A to D are also called information memory.
• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required.
• Flash content integrity check with marginal read modes.

5.9 Peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to MSP430x2xx Family User's Guide (SLAU144).

5.10 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12 conversionmemory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.

5.11 Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very low power, low frequency oscillator and an internal digitally-controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 μs. The basic clock module provides the following clock signals:

• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator for –55°C to 105°C operation. For > 105°C, use external clock source.
• Main clock (MCLK), the system clock used by the CPU
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules

The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.

5.12 Brownout, Supply Voltage Supervisor (SVS)

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The SVS circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM) (the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, V_CC may not have ramped to V_CC(min) at that time. The user must ensure that the default DCO settings are not changed until VCC reaches V_CC(min). If desired, the SVS circuit can be used to determine when V_CC reaches V_CC(min).

5.13 Digital I/O

There are six 8-bit I/O ports implemented – ports P1 through P6:

• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all the eight bits of port P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.

5.14 WDT+ Watchdog Timer

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.

5.15 Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs 16 × 16,
16 × 8, 8 × 16, and 8 × 8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.

5.16 USCI

The universal serial communication interface (USCI) module is used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I²C and asynchronous communication protocols like UART, enhanced UART with automatic baud-rate detection (LIN), and IrDA.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA.

USCI_B0 provides support for SPI (3 or 4 pin) and I²C.

5.17 Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

5.18 Timer_B7

Timer_B7 is a 16-bit timer/counter with three capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

5.19 Comparator_A+

The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.

5.20 ADC12

The ADC12 module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.

5.21 DAC12

The DAC12 module is a 12-bit, R-ladder, voltage-output digital-to-analog converter (DAC). The DAC12 may be used in 8-bit or 12-bit mode and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous operation.

5.22 Peripheral File Map