SLAS619R August   2010  – September 2018 MSP430F5131 , MSP430F5132 , MSP430F5151 , MSP430F5152 , MSP430F5171 , MSP430F5172

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.5, P3.2 to P3.7, and PJ.0 to PJ.6)
    8. 5.8  Schmitt-Trigger Inputs – General-Purpose I/O (P1.6 and P1.7, P2.0 to P2.7, and P3.0 and P3.1)
    9. 5.9  Inputs – Ports P1 and P2
    10. 5.10 Leakage Current – General-Purpose I/O
    11. 5.11 Outputs – Ports P1, P3, PJ (Full Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6)
    12. 5.12 Outputs – Ports P1 to P3 (Full Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
    13. 5.13 Outputs – Ports P1, P3, PJ (Reduced Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6)
    14. 5.14 Outputs – Ports P1 to P3 (Reduced Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
    15. 5.15 Output Frequency – Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    16. 5.16 Output Frequency – Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    17. 5.17 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    18. 5.18 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    19. 5.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    20. 5.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    21. 5.21 Crystal Oscillator, XT1, Low-Frequency Mode
    22. 5.22 Crystal Oscillator, XT1, High-Frequency Mode
    23. 5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 5.24 Internal Reference, Low-Frequency Oscillator (REFO)
    25. 5.25 DCO Frequency
    26. 5.26 PMM, Brownout Reset (BOR)
    27. 5.27 PMM, Core Voltage
    28. 5.28 PMM, SVS High Side
    29. 5.29 PMM, SVM High Side
    30. 5.30 PMM, SVS Low Side
    31. 5.31 PMM, SVM Low Side
    32. 5.32 Wake-up Times From Low-Power Modes
    33. 5.33 Timer_A
    34. 5.34 USCI (UART Mode)
    35. 5.35 USCI (SPI Master Mode)
    36. 5.36 USCI (SPI Slave Mode)
    37. 5.37 USCI (I2C Mode)
    38. 5.38 10-Bit ADC, Power Supply and Input Range Conditions (MSP430F51x2 Devices Only)
    39. 5.39 10-Bit ADC, Timing Parameters (MSP430F51x2 Devices Only)
    40. 5.40 10-Bit ADC, Linearity Parameters (MSP430F51x2 Devices Only)
    41. 5.41 REF, External Reference (MSP430F51x2 Devices Only)
    42. 5.42 REF, Built-In Reference (MSP430F51x2 Devices Only)
    43. 5.43 Comparator_B
    44. 5.44 Timer_D, Power Supply and Reference Clock
    45. 5.45 Timer_D, Local Clock Generator Frequency
    46. 5.46 Timer_D, Trimmed Clock Frequencies
    47. 5.47 Timer_D, Frequency Multiplication Mode
    48. 5.48 Timer_D, Input Capture and Output Compare Timing
    49. 5.49 Flash Memory
    50. 5.50 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  Flash Memory
    8. 6.8  RAM
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
      2. 6.9.2  Port Mapping Controller
      3. 6.9.3  Oscillator and System Clock
      4. 6.9.4  Power-Management Module (PMM)
      5. 6.9.5  Hardware Multiplier
      6. 6.9.6  Watchdog Timer (WDT_A)
      7. 6.9.7  System Module (SYS)
      8. 6.9.8  DMA Controller
      9. 6.9.9  Universal Serial Communication Interface (USCI)
      10. 6.9.10 TA0
      11. 6.9.11 TD0
      12. 6.9.12 TD1
      13. 6.9.13 Comparator_B
      14. 6.9.14 ADC10_A (MSP430F51x2 Only)
      15. 6.9.15 CRC16
      16. 6.9.16 Reference (REF) Module Voltage Reference
      17. 6.9.17 Embedded Emulation Module (EEM) (S Version)
      18. 6.9.18 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.5) Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1 (P1.6 to P1.7) Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      4. 6.10.4  Port P3 (P3.0 and P3.1) Input/Output With Schmitt Trigger
      5. 6.10.5  Port P3 (P3.2 and P3.3) Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3 (P3.4) Input/Output With Schmitt Trigger
      7. 6.10.7  Port P3 (P3.5) Input/Output With Schmitt Trigger
      8. 6.10.8  Port P3 (P3.6) Input/Output With Schmitt Trigger
      9. 6.10.9  Port P3 (P3.7) Input/Output With Schmitt Trigger
      10. 6.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      11. 6.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
      12. 6.10.12 Port J (PJ.4) Input/Output With Schmitt Trigger
      13. 6.10.13 Port J (PJ.5) Input/Output With Schmitt Trigger
      14. 6.10.14 Port J (PJ.6) Input/Output With Schmitt Trigger
    11. 6.11 Device Descriptors
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9.18 Peripheral File Map

Table 6-13 lists the base address and offset range for the registers of all peripherals.

Table 6-13 Peripherals

MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE
Special Functions (see Table 6-14) 0100h 000h–01Fh
PMM (see Table 6-15) 0120h 000h–010h
Flash Control (see Table 6-16) 0140h 000h–00Fh
CRC16 (see Table 6-17) 0150h 000h–007h
RAM Control (see Table 6-18) 0158h 000h–001h
Watchdog (see Table 6-19) 015Ch 000h–001h
UCS (see Table 6-20) 0160h 000h–01Fh
SYS (see Table 6-21) 0180h 000h–01Fh
Shared Reference (see Table 6-22) 01B0h 000h–001h
Port Mapping Control (see Table 6-23) 01C0h 000h–007h
Port Mapping Port P1 (see Table 6-24) 01C8h 000h–007h
Port Mapping Port P2 (see Table 6-25) 01D0h 000h–007h
Port Mapping Port P3 (see Table 6-26) 01D8h 000h–007h
Port P1, P2 (see Table 6-27) 0200h 000h–01Fh
Port P3 (see Table 6-28) 0220h 000h–01Fh
Port PJ (see Table 6-29) 0320h 000h–01Fh
TA0 (see Table 6-30) 03C0h 000h–03Fh
32-Bit Hardware Multiplier (see Table 6-31) 04C0h 000h–02Fh
DMA General Control (see Table 6-32) 0500h 000h–00Fh
DMA Channel 0 (see Table 6-33) 0500h 010h–00Ah
DMA Channel 1 (see Table 6-34) 0500h 020h–00Ah
DMA Channel 2 (see Table 6-35) 0500h 030h–00Ah
USCI_A0 (see Table 6-36) 05C0h 000h–01Fh
USCI_B0 (see Table 6-36) 05E0h 000h–01Fh
ADC10_A (see Table 6-38)
(MSP430F51x2 only)		 0740h 000h–01Fh
Comparator_B (see Table 6-39) 08C0h 000h–00Fh
TD0 (see Table 6-40) 0B00h 000h–03Fh
TEC0 (see Table 6-42) 0C00h 000h–007h
TD1 (see Table 6-41) 0B40h 000h–03Fh
TEC1 (see Table 6-43) 0C20h 000h–007h

Table 6-14 Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION REGISTER OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h

Table 6-15 PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION REGISTER OFFSET
PMM control 0 PMMCTL0 00h
PMM control 1 PMMCTL1 02h
SVS high-side control SVSMHCTL 04h
SVS low-side control SVSMLCTL 06h
PMM interrupt flags PMMIFG 0Ch
PMM interrupt enable PMMIE 0Eh
PMM power mode 5 control PM5CTL0 10h

Table 6-16 Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION REGISTER OFFSET
Flash control 1 FCTL1 00h
Flash control 3 FCTL3 04h
Flash control 4 FCTL4 06h

Table 6-17 CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION REGISTER OFFSET
CRC data input CRC16DI 00h
CRC result CRC16INIRES 04h

Table 6-18 RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION REGISTER OFFSET
RAM control 0 RCCTL0 00h

Table 6-19 Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION REGISTER OFFSET
Watchdog timer control WDTCTL 00h

Table 6-20 UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION REGISTER OFFSET
UCS control 0 UCSCTL0 00h
UCS control 1 UCSCTL1 02h
UCS control 2 UCSCTL2 04h
UCS control 3 UCSCTL3 06h
UCS control 4 UCSCTL4 08h
UCS control 5 UCSCTL5 0Ah
UCS control 6 UCSCTL6 0Ch
UCS control 7 UCSCTL7 0Eh
UCS control 8 UCSCTL8 10h

Table 6-21 SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION REGISTER OFFSET
System control SYSCTL 00h
Bootloader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
Bus error vector generator SYSBERRIV 18h
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh

Table 6-22 Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION REGISTER OFFSET
Shared reference control REFCTL 00h

Table 6-23 Port Mapping Control (Base Address: 01C0h)

REGISTER DESCRIPTION REGISTER OFFSET
Port mapping password PMAPPWD 00h
Port mapping control PMAPCTL 02h

Table 6-24 Port Mapping for Port P1 (Base Address: 01C8h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P1.0 mapping P1MAP0 00h
Port P1.1 mapping P1MAP1 01h
Port P1.2 mapping P1MAP2 02h
Port P1.3 mapping P1MAP3 03h
Port P1.4 mapping P1MAP4 04h
Port P1.5 mapping P1MAP5 05h
Port P1.6 mapping P1MAP6 06h
Port P1.7 mapping P1MAP7 07h

Table 6-25 Port Mapping for Port P2 (Base Address: 01D0h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P2.0 mapping P2MAP0 00h
Port P2.1 mapping P2MAP2 01h
Port P2.2 mapping P2MAP2 02h
Port P2.3 mapping P2MAP3 03h
Port P2.4 mapping P2MAP4 04h
Port P2.5 mapping P2MAP5 05h
Port P2.6 mapping P2MAP6 06h
Port P2.7 mapping P2MAP7 07h

Table 6-26 Port Mapping for Port P3 (Base Address: 01D8h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P3.0 mapping P3MAP0 00h
Port P3.1 mapping P3MAP1 01h
Port P3.2 mapping P3MAP2 02h
Port P3.3 mapping P3MAP3 03h
Port P3.4 mapping P3MAP4 04h
Port P3.5 mapping P3MAP5 05h
Port P3.6 mapping P3MAP6 06h
Port P3.7 mapping P3MAP7 07h

Table 6-27 Port Registers Port P1, P2 (Base Addresses: 0200h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 resistor enable P1REN 06h
Port P1 drive strength P1DS 08h
Port P1 selection P1SEL 0Ah
Port P1 interrupt vector word P1IV 0Eh
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 input P2IN 01h
Port P2 output P2OUT 03h
Port P2 direction P2DIR 05h
Port P2 resistor enable P2REN 07h
Port P2 drive strength P2DS 09h
Port P2 selection P2SEL 0Bh
Port P2 interrupt vector word P2IV 1Eh
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt flag P2IFG 1Dh

Table 6-28 Port Registers P3 (Base Addresses: 0220h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P3 input P3IN 00h
Port P3 output P3OUT 02h
Port P3 direction P3DIR 04h
Port P3 resistor enable P3REN 06h
Port P3 drive strength P3DS 08h
Port P3 selection P3SEL 0Ah

Table 6-29 Port Registers PJ (Base Addresses: 0320h)

REGISTER DESCRIPTION REGISTER OFFSET
Port PJ input PJIN 00h
Port PJ output PJOUT 02h
Port PJ direction PJDIR 04h
Port PJ resistor enable PJREN 06h
Port PJ drive strength PJDS 08h
Port PJ selection PJSEL 0Ah

Table 6-30 TA0 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION REGISTER OFFSET
TA0 control TA0CTL 00h
Capture/compare control 0 TA0CCTL0 02h
Capture/compare control 1 TA0CCTL1 04h
Capture/compare control 2 TA0CCTL2 06h
TA0 counter TA0R 10h
Capture/compare 0 TA0CCR0 12h
Capture/compare 1 TA0CCR1 14h
Capture/compare 2 TA0CCR2 16h
TA0 expansion 0 TA0EX0 20h
TA0 interrupt vector TA0IV 2Eh

Table 6-31 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION REGISTER OFFSET
16-bit operand 1 – multiply MPY 00h
16-bit operand 1 – signed multiply MPYS 02h
16-bit operand 1 – multiply accumulate MAC 04h
16-bit operand 1 – signed multiply accumulate MACS 06h
16-bit operand 2 OP2 08h
16 × 16 result low word RESLO 0Ah
16 × 16 result high word RESHI 0Ch
16 × 16 sum extension register SUMEXT 0Eh
32-bit operand 1 – multiply low word MPY32L 10h
32-bit operand 1 – multiply high word MPY32H 12h
32-bit operand 1 – signed multiply low word MPYS32L 14h
32-bit operand 1 – signed multiply high word MPYS32H 16h
32-bit operand 1 – multiply accumulate low word MAC32L 18h
32-bit operand 1 – multiply accumulate high word MAC32H 1Ah
32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 – low word OP2L 20h
32-bit operand 2 – high word OP2H 22h
32 × 32 result 0 – least significant word RES0 24h
32 × 32 result 1 RES1 26h
32 × 32 result 2 RES2 28h
32 × 32 result 3 – most significant word RES3 2Ah
MPY32 control 0 MPY32CTL0 2Ch

Table 6-32 DMA General Control (Base Address: 0500h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA module control 0 DMACTL0 00h
DMA module control 1 DMACTL1 02h
DMA module control 2 DMACTL2 04h
DMA module control 3 DMACTL3 06h
DMA module control 4 DMACTL4 08h
DMA interrupt vector DMAIV 0Eh

Table 6-33 DMA Channel 0 (Base Address: 0510h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 0 control DMA0CTL 00h
DMA channel 0 source address low DMA0SAL 02h
DMA channel 0 source address high DMA0SAH 04h
DMA channel 0 destination address low DMA0DAL 06h
DMA channel 0 destination address high DMA0DAH 08h
DMA channel 0 transfer size DMA0SZ 0Ah

Table 6-34 DMA Channel 1 (Base Address: 0520h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 1 control DMA1CTL 00h
DMA channel 1 source address low DMA1SAL 02h
DMA channel 1 source address high DMA1SAH 04h
DMA channel 1 destination address low DMA1DAL 06h
DMA channel 1 destination address high DMA1DAH 08h
DMA channel 1 transfer size DMA1SZ 0Ah

Table 6-35 DMA Channel 2 (Base Address: 0530h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 2 control DMA2CTL 00h
DMA channel 2 source address low DMA2SAL 02h
DMA channel 2 source address high DMA2SAH 04h
DMA channel 2 destination address low DMA2DAL 06h
DMA channel 2 destination address high DMA2DAH 08h
DMA channel 2 transfer size DMA2SZ 0Ah

Table 6-36 USCI0_A Registers (Base Address: 05C0h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI control 0 UCA0CTL0 01h
USCI control 1 UCA0CTL1 00h
USCI baud rate 0 UCA0BR0 06h
USCI baud rate 1 UCA0BR1 07h
USCI modulation control UCA0MCTL 08h
USCI status UCA0STAT 0Ah
USCI receive buffer UCA0RXBUF 0Ch
USCI transmit buffer UCA0TXBUF 0Eh
USCI LIN control UCA0ABCTL 10h
USCI IrDA transmit control UCA0IRTCTL 12h
USCI IrDA receive control UCA0IRRCTL 13h
USCI interrupt enable UCA0IE 1Ch
USCI interrupt flags UCA0IFG 1Dh
USCI interrupt vector word UCA0IV 1Eh

Table 6-37 USCI0_B Registers (Base Address: 05E0h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 0 UCB0CTL0 00h
USCI synchronous control 1 UCB0CTL1 01h
USCI synchronous bit rate 0 UCB0BR0 06h
USCI synchronous bit rate 1 UCB0BR1 07h
USCI synchronous status UCB0STAT 0Ah
USCI synchronous receive buffer UCB0RXBUF 0Ch
USCI synchronous transmit buffer UCB0TXBUF 0Eh
USCI I2C own address UCB0I2COA 10h
USCI I2C slave address UCB0I2CSA 12h
USCI interrupt enable UCB0IE 1Ch
USCI interrupt flags UCB0IFG 1Dh
USCI interrupt vector word UCB0IV 1Eh

Table 6-38 ADC10_A Registers (MSP430F51x2 Devices Only) (Base Address: 0740h)

REGISTER DESCRIPTION REGISTER OFFSET
ADC10_A control 0 ADC10CTL0 00h
ADC10_A control 1 ADC10CTL1 02h
ADC10_A control 2 ADC10CTL2 04h
ADC10_A window comparator low threshold ADC10LO 06h
ADC10_A window comparator high threshold ADC10HI 08h
ADC10_A memory control register 0 ADC10MCTL0 0Ah
ADC10_A conversion memory register ADC10MEM0 12h
ADC10_A interrupt enable ADC10IE 1Ah
ADC10_A interrupt flags ADC10IGH 1Ch
ADC10_A interrupt vector word ADC10IV 1Eh

Table 6-39 Comparator_B Registers (Base Address: 08C0h)

REGISTER DESCRIPTION REGISTER OFFSET
Comparator_B control 0 CBCTL0 00h
Comparator_B control 1 CBCTL1 02h
Comparator_B control 2 CBCTL2 04h
Comparator_B control 3 CBCTL3 06h
Comparator_B interrupt CBINT 0Ch
Comparator_B interrupt vector word CBIV 0Eh

Table 6-40 TD0 Registers (Base Address: 0B00h)

REGISTER DESCRIPTION REGISTER OFFSET
TD0 control 0 TD0CTL0 00h
TD0 control 1 TD0CTL1 02h
TD0 control 2 TD0CTL2 04h
TD0 counter TD0R 06h
Capture/compare control 0 TD0CCTL0 08h
Capture/compare 0 TD0CCR0 0Ah
Capture/compare latch 0 TD0CL0 0Ch
Capture/compare control 1 TD0CCTL1 0Eh
Capture/compare 1 TD0CCR1 10h
Capture/compare latch 1 TD0CL1 12h
Capture/compare control 2 TD0CCTL2 14h
Capture/compare 2 TD0CCR2 16h
Capture/compare latch 2 TD0CL2 18h
TD0 high-resolution control 0 TD0HCTL0 38h
TD0 high-resolution control 1 TD0HCTL1 3Ah
TD0 high-resolution interrupt TD0HINT 3Ch
TD0 interrupt vector TD0IV 3Eh

Table 6-41 TD1 Registers (Base Address: 0B40h)

REGISTER DESCRIPTION REGISTER OFFSET
TD1 control 0 TD1CTL0 00h
TD1 control 1 TD1CTL1 02h
TD1 control 2 TD1CTL2 04h
TD1 counter TD1R 06h
Capture/compare control 0 TD1CCTL0 08h
Capture/compare 0 TD1CCR0 0Ah
Capture/compare latch 0 TD1CL0 0Ch
Capture/compare control 1 TD1CCTL1 0Eh
Capture/compare 1 TD1CCR1 10h
Capture/compare latch 1 TD1CL1 12h
Capture/compare control 2 TD1CCTL2 14h
Capture/compare 2 TD1CCR2 16h
Capture/compare latch 2 TD1CL2 18h
TD1 high-resolution control 0 TD1HCTL0 38h
TD1 high-resolution control 1 TD1HCTL1 3Ah
TD1 high-resolution interrupt TD1HINT 3Ch
TD1 interrupt vector TD1IV 3Eh

Table 6-42 TEC0 Registers (Base Address: 0C00h)

REGISTER DESCRIPTION REGISTER OFFSET
Timer event control 0 external control 0 TEC0CTL0 00h
Timer event control 0 external control TEC0CTL1 02h
Timer event control 0 external control TEC0CTL2 04h
Timer event control 0 status TEC0STA 06h
Timer event control 0 external interrupt TEC0XINT 08h
Timer event control 0 external interrupt vector TEC0IV 0Ah

Table 6-43 TEC1 Registers (Base Address: 0C20h)

REGISTER DESCRIPTION REGISTER OFFSET
Timer event control 1 external control 0 TEC1CTL0 00h
Timer event control 1 external control TEC1CTL1 02h
Timer event control 1 external control TEC1CTL2 04h
Timer event control 1 status TEC1STA 06h
Timer event control 1 external interrupt TEC1XINT 08h
Timer event control 1 external interrupt vector TEC1IV 0Ah