SLAS619R August   2010  – September 2018 MSP430F5131 , MSP430F5132 , MSP430F5151 , MSP430F5152 , MSP430F5171 , MSP430F5172

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.5, P3.2 to P3.7, and PJ.0 to PJ.6)
    8. 5.8  Schmitt-Trigger Inputs – General-Purpose I/O (P1.6 and P1.7, P2.0 to P2.7, and P3.0 and P3.1)
    9. 5.9  Inputs – Ports P1 and P2
    10. 5.10 Leakage Current – General-Purpose I/O
    11. 5.11 Outputs – Ports P1, P3, PJ (Full Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6)
    12. 5.12 Outputs – Ports P1 to P3 (Full Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
    13. 5.13 Outputs – Ports P1, P3, PJ (Reduced Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6)
    14. 5.14 Outputs – Ports P1 to P3 (Reduced Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
    15. 5.15 Output Frequency – Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    16. 5.16 Output Frequency – Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    17. 5.17 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    18. 5.18 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    19. 5.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    20. 5.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    21. 5.21 Crystal Oscillator, XT1, Low-Frequency Mode
    22. 5.22 Crystal Oscillator, XT1, High-Frequency Mode
    23. 5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 5.24 Internal Reference, Low-Frequency Oscillator (REFO)
    25. 5.25 DCO Frequency
    26. 5.26 PMM, Brownout Reset (BOR)
    27. 5.27 PMM, Core Voltage
    28. 5.28 PMM, SVS High Side
    29. 5.29 PMM, SVM High Side
    30. 5.30 PMM, SVS Low Side
    31. 5.31 PMM, SVM Low Side
    32. 5.32 Wake-up Times From Low-Power Modes
    33. 5.33 Timer_A
    34. 5.34 USCI (UART Mode)
    35. 5.35 USCI (SPI Master Mode)
    36. 5.36 USCI (SPI Slave Mode)
    37. 5.37 USCI (I2C Mode)
    38. 5.38 10-Bit ADC, Power Supply and Input Range Conditions (MSP430F51x2 Devices Only)
    39. 5.39 10-Bit ADC, Timing Parameters (MSP430F51x2 Devices Only)
    40. 5.40 10-Bit ADC, Linearity Parameters (MSP430F51x2 Devices Only)
    41. 5.41 REF, External Reference (MSP430F51x2 Devices Only)
    42. 5.42 REF, Built-In Reference (MSP430F51x2 Devices Only)
    43. 5.43 Comparator_B
    44. 5.44 Timer_D, Power Supply and Reference Clock
    45. 5.45 Timer_D, Local Clock Generator Frequency
    46. 5.46 Timer_D, Trimmed Clock Frequencies
    47. 5.47 Timer_D, Frequency Multiplication Mode
    48. 5.48 Timer_D, Input Capture and Output Compare Timing
    49. 5.49 Flash Memory
    50. 5.50 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  Flash Memory
    8. 6.8  RAM
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
      2. 6.9.2  Port Mapping Controller
      3. 6.9.3  Oscillator and System Clock
      4. 6.9.4  Power-Management Module (PMM)
      5. 6.9.5  Hardware Multiplier
      6. 6.9.6  Watchdog Timer (WDT_A)
      7. 6.9.7  System Module (SYS)
      8. 6.9.8  DMA Controller
      9. 6.9.9  Universal Serial Communication Interface (USCI)
      10. 6.9.10 TA0
      11. 6.9.11 TD0
      12. 6.9.12 TD1
      13. 6.9.13 Comparator_B
      14. 6.9.14 ADC10_A (MSP430F51x2 Only)
      15. 6.9.15 CRC16
      16. 6.9.16 Reference (REF) Module Voltage Reference
      17. 6.9.17 Embedded Emulation Module (EEM) (S Version)
      18. 6.9.18 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.5) Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1 (P1.6 to P1.7) Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      4. 6.10.4  Port P3 (P3.0 and P3.1) Input/Output With Schmitt Trigger
      5. 6.10.5  Port P3 (P3.2 and P3.3) Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3 (P3.4) Input/Output With Schmitt Trigger
      7. 6.10.7  Port P3 (P3.5) Input/Output With Schmitt Trigger
      8. 6.10.8  Port P3 (P3.6) Input/Output With Schmitt Trigger
      9. 6.10.9  Port P3 (P3.7) Input/Output With Schmitt Trigger
      10. 6.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      11. 6.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
      12. 6.10.12 Port J (PJ.4) Input/Output With Schmitt Trigger
      13. 6.10.13 Port J (PJ.5) Input/Output With Schmitt Trigger
      14. 6.10.14 Port J (PJ.6) Input/Output With Schmitt Trigger
    11. 6.11 Device Descriptors
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.2 Signal Descriptions

Table 4-1 describes the signals for all device and package variants.

Table 4-1 Signal Descriptions

TERMINAL I/O(1) DESCRIPTION
NAME NO.(3)
RSB DA YFF
P1.0/
PM_UCA0CLK/
<br/>
PM_UCB0STE/
A0(4)/
CB0		 1 5 B5 I/O General-purpose digital I/O with reconfigurable port mapping secondary function(2)
Default mapping: Clock signal input – USCI_A0 SPI slave mode; Clock signal output – USCI_A0 SPI master mode
Default mapping: Slave transmit enable – USCI_B0 SPI mode
Analog input A0 – 10-bit ADC(4)
Comparator_B Input 0
P1.1/
PM_UCA0TXD/
PM_UCA0SIMO/
A1(4)/
CB1		 2 6 B6 I/O General-purpose digital I/O
Default mapping: Transmit data – USCI_A0 UART mode
Default mapping: Slave in, master out – USCI_A0 SPI mode
Analog input A1 – 10-bit ADC(4)
Comparator_B Input 1
P1.2/
PM_UCA0RXD/
PM_UCA0SOMI/
A2(4)/
CB2		 3 7 C5 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Receive data – USCI_A0 UART mode
Default mapping: Slave out, master in – USCI_A0 SPI mode
Analog input A2 – 10-bit ADC(4)
Comparator_B Input 2
P1.3/
PM_UCB0CLK/
<br/>
PM_UCA0STE/
A3(4)/
CB3		 4 8 C6 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Clock signal input – USCI_B0 SPI slave mode; Clock signal output – USCI_B0 SPI master mode
Default mapping: Slave transmit enable – USCI_A0 SPI mode
Analog input A3 – 10-bit ADC(4)
Comparator_B Input 3
P1.4/
PM_UCB0SIMO/
PM_UCB0SDA/
A4(4)/
CB4		 5 9 D5 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave in, master out – USCI_B0 SPI mode
Default mapping: I2C data – USCI_B0 I2C mode
Analog input A4 – 10-bit ADC(4)
Comparator_B Input 4
P1.5/
PM_UCB0SOMI/
PM_UCB0SCL/
A5(4)/
CB5		 6 10 D6 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave out, master in – USCI_B0 SPI mode
Default mapping: I2C clock – USCI_B0 I2C mode
Analog input A5 – 10-bit ADC(4)
Comparator_B Input 5
PJ.0/
SMCLK/
TDO/
CB6		 7 11 E6 I/O General-purpose digital I/O
SMCLK clock output
Test data output port
Comparator_B Input 6
PJ.1/
MCLK/
TDI/TCLK/
CB7		 8 12 E5 I/O General-purpose digital I/O
MCLK clock output
Test data input or test clock input
Comparator_B Input 7
PJ.2/
ADC10CLK/
TMS/
CB8		 9 13 F6 I/O General-purpose digital I/O
ADC10_A clock output
Test mode select
Comparator_B Input 8
PJ.3/
ACLK/
TCK/
CB9		 10 14 E4 I/O General-purpose digital I/O
ACLK output port
Test clock
Comparator_B Input 9
P1.6/
PM_TD0.0		 11 15 G6 I/O, DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 CCR0 compare output/capture input
P1.7/
PM_TD0.1		 12 16 F5 I/O, DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 CCR1 compare output/capture input
P2.0/
PM_TD0.2		 13 17 F4 I/O, DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 CCR2 compare output/capture input
P2.1/
PM_TD1.0		 14 18 G5 I/O, DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 CCR0 compare output/capture input
P2.2/
PM_TD1.1		 15 19 G4 I/O, DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 CCR1 compare output/capture input
P2.3/
PM_TD1.2		 16 20 E3 I/O, DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 CCR2 compare output/capture input
DVIO 17 21 G3 5-V tolerant digital I/O power supply
DVSS 18 22 G2 Digital ground supply
P2.4/
PM_TEC0CLR/
PM_TEC0FLT2/
PM_TD0.0		 19 23 F3 I/O, DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 external clear input
Default mapping: TD0 fault input channel 2 (controlled by module input enable)
Default mapping: TD0 CCR0 compare output
P2.5/
PM_TEC0FLT0/
PM_TD0.1		 20 24 G1 I/O, DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 fault input channel 0
Default mapping: TD0 CCR1 compare output
P2.6/
PM_TEC0FLT1/
PM_TD0.2		 21 25 F2 I/O, DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 fault input channel 1
Default mapping: TD0 CCR2 compare output
P2.7/
PM_TEC1CLR/
PM_TEC1FLT1/
PM_TD1.0		 22 26 E2 I/O, DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 external clear
Default mapping: TD1 fault input channel 1 (controlled by module input enable)
Default mapping: TD1 CCR0 compare output
P3.0/
PM_TEC1FLT2/
PM_TD1.1		 23 27 F1 I/O, DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 fault input channel 2
Default mapping: TD1 CCR1 compare output
P3.1/
PM_TEC1FLT0/
PM_TD1.2		 24 28 E1 I/O, DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 fault input channel 0
Default mapping: TD1 CCR2 compare output
VCORE 25 29 D1 Regulated core power supply
DVSS 26 30 C1 Digital ground supply
DVCC 27 31 B1 Digital power supply
PJ.6/
TD1CLK/
TD0.1/
CB15		 28 32 C2 I/O General-purpose digital I/O
TD1 clock input
TD0 CCR1 compare output
Comparator_B Input 15
P3.2/
PM_TD0.0/
PM_SMCLK/
CB14		 29 33 B2 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 CCR0 capture input
Default mapping: SMCLK output
Comparator_B Input 14
P3.3/
PM_TA0CLK/
PM_CBOUT/
CB13		 30 34 A1 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TA0 clock input
Default mapping: Comparator_B output
Comparator_B Input 13
P3.4/
PM_TD0CLK/
PM_MCLK		 31 – A2 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 clock input
Default mapping: MCLK output
TEST/
SBWTCK		 32 35 D2 Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
RST/
NMI/
SBWTDIO		 33 36 B3 Reset input active low(5)
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
P3.5/
PM_TA0.2/
A8(4)
VEREF+/
CB12		 34 37 A3 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TA0 CCR2 compare output/capture input
Analog input A8 – 10-bit ADC(4)
Positive terminal for the ADC reference voltage for an external applied reference voltage
Comparator_B Input 12
P3.6/
PM_TA0.1/
A7(4)/
VEREF-/
CB11		 35 38 A4 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TA0 CCR1 compare output/capture input
Analog input A7 – 10-bit ADC(4)
Negative terminal for the ADC reference voltage for an external applied reference voltage
Comparator_B Input 11
P3.7/
PM_TA0.0/
A6(4)/
CB10		 36 – B4 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TA0 CCR0 compare output/capture input
Analog input A6 – 10-bit ADC(4)
Comparator_B Input 10
AVCC 37 1 C3 Analog power supply
PJ.4/
XOUT		 38 2 A5 I/O General-purpose digital I/O
Output terminal of crystal oscillator
PJ.5/
XIN		 39 3 A6 I/O General-purpose digital I/O
Input terminal for crystal oscillator
AVSS 40 4 C4 Analog ground supply
QFN pad – NA NA Recommended to connect to DVSS externally
(1) I = input, O = output
(2) For details on the Port Mapping Controller, see Section 6.9.2.
(3) N/A = not available on this package offering
(4) The ADC10_A module is available on MSP430F51x2 devices. The secondary pin functions Ax (ADC10_A channel x) available only in MSP430F51x2 devices.
(5) When this pin is configured as reset, the internal pullup resistor is enabled by default.