SLAS718H November   2012  – September 2018 MSP430F5212 , MSP430F5214 , MSP430F5217 , MSP430F5219 , MSP430F5222 , MSP430F5224 , MSP430F5229

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Terminal Functions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC)
    8. 5.8  Schmitt-Trigger Inputs – General-Purpose I/O DVIO Domain (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN)
    9. 5.9  Inputs – Interrupts DVCC Domain Port P1 (P1.0 to P1.3)
    10. 5.10 Inputs – Interrupts DVIO Domain Ports P1 and P2 (P1.4 to P1.7, P2.0 to P2.7)
    11. 5.11 Leakage Current – General-Purpose I/O DVCC Domain (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    12. 5.12 Leakage Current – General-Purpose I/O DVIO Domain (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    13. 5.13 Outputs – General-Purpose I/O DVCC Domain (Full Drive Strength) (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    14. 5.14 Outputs – General-Purpose I/O DVCC Domain (Reduced Drive Strength) (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    15. 5.15 Outputs – General-Purpose I/O DVIO Domain (Full Drive Strength) (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    16. 5.16 Outputs – General-Purpose I/O DVIO Domain (Reduced Drive Strength) (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    17. 5.17 Output Frequency – General-Purpose I/O DVCC Domain (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    18. 5.18 Output Frequency – General-Purpose I/O DVIO Domain (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    19. 5.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    20. 5.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    21. 5.21 Crystal Oscillator, XT1, Low-Frequency Mode
    22. 5.22 Crystal Oscillator, XT2
    23. 5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 5.24 Internal Reference, Low-Frequency Oscillator (REFO)
    25. 5.25 DCO Frequency
    26. 5.26 PMM, Brownout Reset (BOR)
    27. 5.27 PMM, Core Voltage
    28. 5.28 PMM, SVS High Side
    29. 5.29 PMM, SVM High Side
    30. 5.30 PMM, SVS Low Side
    31. 5.31 PMM, SVM Low Side
    32. 5.32 Wake-up Times From Low-Power Modes and Reset
    33. 5.33 Timer_A
    34. 5.34 Timer_B
    35. 5.35 USCI (UART Mode), Recommended Operating Conditions
    36. 5.36 USCI (UART Mode)
    37. 5.37 USCI (SPI Master Mode), Recommended Operating Conditions
    38. 5.38 USCI (SPI Master Mode)
    39. 5.39 USCI (SPI Slave Mode)
    40. 5.40 USCI (I2C Mode)
    41. 5.41 10-Bit ADC, Power Supply and Input Range Conditions
    42. 5.42 10-Bit ADC, Timing Parameters
    43. 5.43 10-Bit ADC, Linearity Parameters
    44. 5.44 REF, External Reference
    45. 5.45 REF, Built-In Reference
    46. 5.46 Comparator_B
    47. 5.47 Flash Memory
    48. 5.48 JTAG and Spy-Bi-Wire Interface
    49. 5.49 DVIO BSL Entry
  6. 6Detailed Description
    1. 6.1  CPU (Link to user's guide)
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory (Link to user's guide)
    8. 6.8  RAM (Link to user's guide)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O (Link to user's guide)
      2. 6.9.2  Port Mapping Controller (Link to user's guide)
      3. 6.9.3  Oscillator and System Clock (Link to user's guide)
      4. 6.9.4  Power-Management Module (PMM) (Link to user's guide)
      5. 6.9.5  Hardware Multiplier (Link to user's guide)
      6. 6.9.6  Real-Time Clock (RTC_A) (Link to user's guide)
      7. 6.9.7  Watchdog Timer (WDT_A) (Link to user's guide)
      8. 6.9.8  System Module (SYS) (Link to user's guide)
      9. 6.9.9  DMA Controller (Link to user's guide)
      10. 6.9.10 Universal Serial Communication Interface (USCI) (Links to user's guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.9.11 TA0 (Link to user's guide)
      12. 6.9.12 TA1 (Link to user's guide)
      13. 6.9.13 TA2 (Link to user's guide)
      14. 6.9.14 TB0 (Link to user's guide)
      15. 6.9.15 Comparator_B (Link to user's guide)
      16. 6.9.16 ADC10_A (Link to user's guide)
      17. 6.9.17 CRC16 (Link to user's guide)
      18. 6.9.18 REF Voltage Reference (Link to user's guide)
      19. 6.9.19 Embedded Emulation Module (EEM) (S Version) (Link to user's guide)
      20. 6.9.20 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.10.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 6.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5 (P5.2) Input/Output With Schmitt Trigger
      7. 6.10.7  Port P5 (P5.3) Input/Output With Schmitt Trigger
      8. 6.10.8  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      9. 6.10.9  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      10. 6.10.10 Port P7 (P7.0 to P7.5) Input/Output With Schmitt Trigger
      11. 6.10.11 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      12. 6.10.12 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11 Device Descriptors
  7. 7Device and Documentation Support
    1. 7.1 Getting Started
    2. 7.2 Device Nomenclature
    3. 7.3 Tools and Software
    4. 7.4 Documentation Support
    5. 7.5 Related Links
    6. 7.6 Community Resources
    7. 7.7 Trademarks
    8. 7.8 Electrostatic Discharge Caution
    9. 7.9 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Documentation Support

The following documents describe the MSP430F522x and MSP430F521x MCUs. Copies of these documents are available on the Internet at www.ti.com.

Receiving Notification of Document Updates

To receive notification of documentation updates—including silicon errata—go to the product folder for your device on ti.com (see Section 7.5 for links to product folders). In the upper right corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any revised document.

Errata

User's Guides

    MSP430 Flash Device Bootloader (BSL) User's Guide

    The MSP430 bootloader (BSL) (formerly known as the bootstrap loader) lets users communicate with embedded memory in the MSP430 microcontroller during the prototyping phase, final production, and in service. Both the programmable memory (flash memory) and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap loader programs found in some digital signal processors (DSPs) that automatically load program code (and data) from external memory to the internal memory of the DSP.

    MSP430 Programming With the JTAG Interface

    This document describes the functions that are required to erase, program, and verify the memory module of the MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition, it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).

    MSP430 Hardware Tools User's Guide

    This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultra-low-power microcontroller.

Application Reports

    Designing with MSP430F522x and MSP430F521x Devices

    The MSP430F522x and MSP430F521x devices support a split supply I/O system that is essential in systems in which the MCU is required to interface with external devices (such as sensors or other processors) that operate at different voltage level compared to the MCU device supply. Additionally, the split supply input voltage range of the F522x and F521x devices starts as low as 1.62 V (see the device data sheet specifications), and this allows for nominal 1.8-V I/O interface without the need for external level translation. This application report describes the various design considerations to keep in mind while designing the F522x and F521x devices in an application.

    General Oversampling of MSP ADCs for Higher Resolution

    Multiple MSP ultra-low-power microcontrollers offer analog-to-digital converters (ADCs) to convert physical quantities into digital numbers, a function that is widely used across numerous applications. There are times, however, when a customer design demands a higher resolution than the ADC of the selected MSP can offer. This application report, which is based on the previously-published Oversampling the ADC12 for Higher Resolution (SLAA323), therefore describes how an oversampling method can be incorporated to increase ADC resolution past the currently available number of bits.

    MSP430 32-kHz Crystal Oscillators

    Selection of the correct crystal, correct load circuit, and proper board layout are important for a stable crystal oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout are given. The document also contains detailed information on the possible oscillator tests to ensure stable oscillator operation in mass production.

    MSP430 System-Level ESD Considerations

    System-Level ESD has become increasingly demanding as silicon technology scales to lower voltages and the need for designing cost-effective and ultra-low-power components. This application report addresses three ESD topics to help board designers and OEMs understand and design robust system-level designs: (1) Component-level ESD testing and system-level ESD testing; (2) General design guidelines for system-level ESD protection; (3) Introduction to System Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip ESD protection. A few real-world system-level ESD protection design examples and their results are discussed.