SLAS718H November   2012  – September 2018 MSP430F5212 , MSP430F5214 , MSP430F5217 , MSP430F5219 , MSP430F5222 , MSP430F5224 , MSP430F5229

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Terminal Functions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC)
    8. 5.8  Schmitt-Trigger Inputs – General-Purpose I/O DVIO Domain (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN)
    9. 5.9  Inputs – Interrupts DVCC Domain Port P1 (P1.0 to P1.3)
    10. 5.10 Inputs – Interrupts DVIO Domain Ports P1 and P2 (P1.4 to P1.7, P2.0 to P2.7)
    11. 5.11 Leakage Current – General-Purpose I/O DVCC Domain (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    12. 5.12 Leakage Current – General-Purpose I/O DVIO Domain (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    13. 5.13 Outputs – General-Purpose I/O DVCC Domain (Full Drive Strength) (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    14. 5.14 Outputs – General-Purpose I/O DVCC Domain (Reduced Drive Strength) (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    15. 5.15 Outputs – General-Purpose I/O DVIO Domain (Full Drive Strength) (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    16. 5.16 Outputs – General-Purpose I/O DVIO Domain (Reduced Drive Strength) (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    17. 5.17 Output Frequency – General-Purpose I/O DVCC Domain (P1.0 to P1.3, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    18. 5.18 Output Frequency – General-Purpose I/O DVIO Domain (P1.4 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    19. 5.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    20. 5.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    21. 5.21 Crystal Oscillator, XT1, Low-Frequency Mode
    22. 5.22 Crystal Oscillator, XT2
    23. 5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 5.24 Internal Reference, Low-Frequency Oscillator (REFO)
    25. 5.25 DCO Frequency
    26. 5.26 PMM, Brownout Reset (BOR)
    27. 5.27 PMM, Core Voltage
    28. 5.28 PMM, SVS High Side
    29. 5.29 PMM, SVM High Side
    30. 5.30 PMM, SVS Low Side
    31. 5.31 PMM, SVM Low Side
    32. 5.32 Wake-up Times From Low-Power Modes and Reset
    33. 5.33 Timer_A
    34. 5.34 Timer_B
    35. 5.35 USCI (UART Mode), Recommended Operating Conditions
    36. 5.36 USCI (UART Mode)
    37. 5.37 USCI (SPI Master Mode), Recommended Operating Conditions
    38. 5.38 USCI (SPI Master Mode)
    39. 5.39 USCI (SPI Slave Mode)
    40. 5.40 USCI (I2C Mode)
    41. 5.41 10-Bit ADC, Power Supply and Input Range Conditions
    42. 5.42 10-Bit ADC, Timing Parameters
    43. 5.43 10-Bit ADC, Linearity Parameters
    44. 5.44 REF, External Reference
    45. 5.45 REF, Built-In Reference
    46. 5.46 Comparator_B
    47. 5.47 Flash Memory
    48. 5.48 JTAG and Spy-Bi-Wire Interface
    49. 5.49 DVIO BSL Entry
  6. 6Detailed Description
    1. 6.1  CPU (Link to user's guide)
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory (Link to user's guide)
    8. 6.8  RAM (Link to user's guide)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O (Link to user's guide)
      2. 6.9.2  Port Mapping Controller (Link to user's guide)
      3. 6.9.3  Oscillator and System Clock (Link to user's guide)
      4. 6.9.4  Power-Management Module (PMM) (Link to user's guide)
      5. 6.9.5  Hardware Multiplier (Link to user's guide)
      6. 6.9.6  Real-Time Clock (RTC_A) (Link to user's guide)
      7. 6.9.7  Watchdog Timer (WDT_A) (Link to user's guide)
      8. 6.9.8  System Module (SYS) (Link to user's guide)
      9. 6.9.9  DMA Controller (Link to user's guide)
      10. 6.9.10 Universal Serial Communication Interface (USCI) (Links to user's guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.9.11 TA0 (Link to user's guide)
      12. 6.9.12 TA1 (Link to user's guide)
      13. 6.9.13 TA2 (Link to user's guide)
      14. 6.9.14 TB0 (Link to user's guide)
      15. 6.9.15 Comparator_B (Link to user's guide)
      16. 6.9.16 ADC10_A (Link to user's guide)
      17. 6.9.17 CRC16 (Link to user's guide)
      18. 6.9.18 REF Voltage Reference (Link to user's guide)
      19. 6.9.19 Embedded Emulation Module (EEM) (S Version) (Link to user's guide)
      20. 6.9.20 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.10.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 6.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5 (P5.2) Input/Output With Schmitt Trigger
      7. 6.10.7  Port P5 (P5.3) Input/Output With Schmitt Trigger
      8. 6.10.8  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      9. 6.10.9  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      10. 6.10.10 Port P7 (P7.0 to P7.5) Input/Output With Schmitt Trigger
      11. 6.10.11 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      12. 6.10.12 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11 Device Descriptors
  7. 7Device and Documentation Support
    1. 7.1 Getting Started
    2. 7.2 Device Nomenclature
    3. 7.3 Tools and Software
    4. 7.4 Documentation Support
    5. 7.5 Related Links
    6. 7.6 Community Resources
    7. 7.7 Trademarks
    8. 7.8 Electrostatic Discharge Caution
    9. 7.9 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1 Terminal Functions

TERMINAL I/O(1) SUPPLY DESCRIPTION
NAME NO.
RGC ZQE YFF RGZ
P6.0/CB0/A0 1 A1 C2 46 I/O DVCC General-purpose digital I/O

Comparator_B input CB0

Analog input A0 for ADC (not available on all device types)
P6.1/CB1/A1 2 B2 A1 47 I/O DVCC General-purpose digital I/O

Comparator_B input CB1

Analog input A1 for ADC (not available on all device types)
P6.2/CB2/A2 3 B1 B2 48 I/O DVCC General-purpose digital I/O

Comparator_B input CB2

Analog input A2 for ADC (not available on all device types)
P6.3/CB3/A3 4 C2 C3 1 I/O DVCC General-purpose digital I/O

Comparator_B input CB3

Analog input A3 for ADC (not available on all device types)
P6.4/CB4/A4 5 C1 A2 2 I/O DVCC General-purpose digital I/O

Comparator_B input CB4

Analog input A4 for ADC (not available on all device types)
P6.5/CB5/A5 6 D2 B3 3 I/O DVCC General-purpose digital I/O

Comparator_B input CB5

Analog input A5 for ADC (not available on all device types)
P6.6/CB6/A6 7 D1 C4 N/A I/O DVCC General-purpose digital I/O (not available on all device types)

Comparator_B input CB6 (not available on all device types)

Analog input A6 for ADC (not available on all device types)
P6.7/CB7/A7 8 D3 A3 N/A I/O DVCC General-purpose digital I/O (not available on all device types)

Comparator_B input CB7 (not available on all device types)

Analog input A7 for ADC (not available on all device types)
P5.0/A8/VeREF+ 9 E1 B4 4 I/O DVCC General-purpose digital I/O

Analog input A8 for ADC (not available on all device types)

Input for an external reference voltage to the ADC (not available on all device types)
P5.1/A9/VeREF- 10 E2 A4 5 I/O DVCC General-purpose digital I/O

Analog input A9 for ADC (not available on all device types)

Negative terminal for the ADC reference voltage for an external applied reference voltage (not available on all device types)
AVCC 11 F2 B5 6 Analog power supply
P5.4/XIN 12 F1 A5 7 I/O DVCC General-purpose digital I/O

Input terminal for crystal oscillator XT1(6)

P5.5/XOUT 13 G1 A6 8 I/O DVCC General-purpose digital I/O

Output terminal of crystal oscillator XT1
AVSS 14 G2 B6 9 Analog ground supply
DVCC 15 H1 A7 10 Digital power supply
DVSS 16 J1 A8 11 Digital ground supply
VCORE(3) 17 J2 B8 12 DVCC Regulated core power supply output (internal use only, no external current loading)
P1.0/TA0CLK/ACLK 18 H2 B7 13 I/O DVCC General-purpose digital I/O with port interrupt

TA0 clock signal TA0CLK input

ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P1.1/TA0.0 19 H3 C7 14 I/O DVCC General-purpose digital I/O with port interrupt

TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output
P1.2/TA0.1 20 J3 C8 15 I/O DVCC General-purpose digital I/O with port interrupt

TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input
P1.3/TA0.2 21 G4 C6 16 I/O DVCC General-purpose digital I/O with port interrupt

TA0 CCR2 capture: CCI2A input, compare: Out2 output
P1.4/TA0.3 22 H4 C5 17 I/O DVIO(4) General-purpose digital I/O with port interrupt

TA0 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4 23 J4 D8 18 I/O DVIO(4) General-purpose digital I/O with port interrupt

TA0 CCR4 capture: CCI4A input, compare: Out4 output
P1.6/TA1CLK/CBOUT 24 G5 D7 19 I/O DVIO(4) General-purpose digital I/O with port interrupt

TA1 clock signal TA1CLK input

Comparator_B output
P1.7/TA1.0 25 H5 D6 20 I/O DVIO(4) General-purpose digital I/O with port interrupt

TA1 CCR0 capture: CCI0A input, compare: Out0 output
P2.0/TA1.1 26 J5 E8 N/A I/O DVIO(4) General-purpose digital I/O with port interrupt (not available on all device types)

TA1 CCR1 capture: CCI1A input, compare: Out1 output (not available on all device types)
P2.1/TA1.2 27 G6 D5 N/A I/O DVIO(4) General-purpose digital I/O with port interrupt (not available on all device types)

TA1 CCR2 capture: CCI2A input, compare: Out2 output (not available on all device types)
P2.2/TA2CLK/SMCLK 28 J6 E7 N/A I/O DVIO(4) General-purpose digital I/O with port interrupt (not available on all device types)

TA2 clock signal TA2CLK input

SMCLK output (not available on all device types)
P2.3/TA2.0 29 H6 F8 N/A I/O DVIO(4) General-purpose digital I/O with port interrupt (not available on all device types)

TA2 CCR0 capture: CCI0A input, compare: Out0 output (not available on all device types)
P2.4/TA2.1 30 J7 E6 N/A I/O DVIO(4) General-purpose digital I/O with port interrupt (not available on all device types)

TA2 CCR1 capture: CCI1A input, compare: Out1 output (not available on all device types)
P2.5/TA2.2 31 J8 F7 N/A I/O DVIO(4) General-purpose digital I/O with port interrupt (not available on all device types)

TA2 CCR2 capture: CCI2A input, compare: Out2 output (not available on all device types)
P2.6/RTCCLK/DMAE0 32 J9 G8 N/A I/O DVIO(4) General-purpose digital I/O with port interrupt (not available on all device types)

RTC clock output for calibration (not available on all device types)

DMA external trigger input (not available on all device types)
P2.7/UCB0STE/ UCA0CLK 33 H7 F6 21 I/O DVIO(4) General-purpose digital I/O

Slave transmit enable – USCI_B0 SPI mode

Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
P3.0/UCB0SIMO/ UCB0SDA 34 H8 H8 22 I/O DVIO(4) General-purpose digital I/O

Slave in, master out – USCI_B0 SPI mode

I2C data – USCI_B0 I2C mode
P3.1/UCB0SOMI/ UCB0SCL 35 H9 G7 23 I/O DVIO(4) General-purpose digital I/O

Slave out, master in – USCI_B0 SPI mode

I2C clock – USCI_B0 I2C mode
P3.2/UCB0CLK/ UCA0STE 36 G8 G6 24 I/O DVIO(4) General-purpose digital I/O

Clock signal input – USCI_B0 SPI slave mode
Clock signal output – USCI_B0 SPI master mode

Slave transmit enable – USCI_A0 SPI mode
P3.3/UCA0TXD/ UCA0SIMO 37 G9 H7 25 I/O DVIO(4) General-purpose digital I/O

Transmit data – USCI_A0 UART mode

Slave in, master out – USCI_A0 SPI mode
P3.4/UCA0RXD/ UCA0SOMI 38 G7 G5 26 I/O DVIO(4) General-purpose digital I/O

Receive data – USCI_A0 UART mode

Slave out, master in – USCI_A0 SPI mode
DVSS 39 F9 H6 27 Digital ground supply
DVIO(5) 40 E9 H5 28 Digital I/O power supply
P4.0/PM_UCB1STE/ PM_UCA1CLK 41 E8 F5 29 I/O DVIO(4) General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Slave transmit enable – USCI_B1 SPI mode

Default mapping: Clock signal input – USCI_A1 SPI slave mode
Default mapping: Clock signal output – USCI_A1 SPI master mode
P4.1/PM_UCB1SIMO/ PM_UCB1SDA 42 E7 H4 30 I/O DVIO(4) General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: Slave in, master out – USCI_B1 SPI mode

Default mapping: I2C data – USCI_B1 I2C mode
P4.2/PM_UCB1SOMI/ PM_UCB1SCL 43 D9 E5 31 I/O DVIO(4) General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: Slave out, master in – USCI_B1 SPI mode

Default mapping: I2C clock – USCI_B1 I2C mode
P4.3/PM_UCB1CLK/ PM_UCA1STE 44 D8 G4 32 I/O DVIO(4) General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: Clock signal input – USCI_B1 SPI slave mode
Default mapping: Clock signal output – USCI_B1 SPI master mode

Default mapping: Slave transmit enable – USCI_A1 SPI mode
P4.4/PM_UCA1TXD/ PM_UCA1SIMO 45 D7 H3 33 I/O DVIO(4) General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: Transmit data – USCI_A1 UART mode

Default mapping: Slave in, master out – USCI_A1 SPI mode
P4.5/PM_UCA1RXD/ PM_UCA1SOMI 46 C9 F4 34 I/O DVIO(4) General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: Receive data – USCI_A1 UART mode

Default mapping: Slave out, master in – USCI_A1 SPI mode
P4.6/PM_NONE 47 C8 H2 35 I/O DVIO(4) General-purpose digital I/O with reconfigurable port mapping secondary function

Default mapping: no secondary function
P4.7/PM_NONE 48 C7 G3 N/A I/O DVIO(4) General-purpose digital I/O with reconfigurable port mapping secondary function (not available on all device types)

Default mapping: no secondary function (not available on all device types)

P7.0/TB0.0 49 B8, B9 H1 N/A I/O DVIO(4) General-purpose digital I/O (not available on all device types)

TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on all device types)
P7.1/TB0.1 50 A9 G2 N/A I/O DVIO(4) General-purpose digital I/O (not available on all device types)

TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available on all device types)
P7.2/TB0.2 51 B7 F3 N/A I/O DVIO(4) General-purpose digital I/O (not available on all device types)

TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on all device types)
P7.3/TB0.3 52 A8 G1 N/A I/O DVIO(4) General-purpose digital I/O (not available on all device types)

TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on all device types)
P7.4/TB0.4 53 A7 F2 N/A I/O DVIO(4) General-purpose digital I/O (not available on all device types)

TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on all device types)
P7.5/TB0.5 54 A6 F1 N/A I/O DVIO(4) General-purpose digital I/O (not available on all device types)

TB0 CCR5 capture: CCI5A input, compare: Out5 output (not available on all device types)
BSLEN 55 B6 E2 36 I DVIO(4) BSL enable with internal pulldown
RST/NMI 56 A5 E3 37 I DVIO(4) Reset input active low(10)(11)

Nonmaskable interrupt input(10)

P5.2/XT2IN 57 B5 E1 38 I/O DVCC General-purpose digital I/O

Input terminal for crystal oscillator XT2(7)

P5.3/XT2OUT 58 B4 D1 39 I/O DVCC General-purpose digital I/O

Output terminal of crystal oscillator XT2
TEST/SBWTCK(8) 59 A4 E4 40 I DVCC Test mode pin – Selects four wire JTAG operation

Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
PJ.0/TDO(9) 60 C5 D2 41 I/O DVCC General-purpose digital I/O

JTAG test data output port
PJ.1/TDI/TCLK(9) 61 C4 C1 42 I/O DVCC General-purpose digital I/O

JTAG test data input or test clock input
PJ.2/TMS(9) 62 A3 D3 43 I/O DVCC General-purpose digital I/O

JTAG test mode select
PJ.3/TCK(9) 63 B3 B1 44 I/O DVCC General-purpose digital I/O

JTAG test clock
RSTDVCC/ SBWTDIO(9) 64 A2 D4 45 I/O DVCC Reset input, active-low(12)

Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated
Reserved N/A  (2) N/A N/A Reserved
QFN Pad Pad N/A N/A Pad QFN thermal pad. TI recommends connecting to VSS.
(1) I = input, O = output, N/A = not available
(2) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
(3) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE.
(4) This pin function is supplied by DVIO. See Section 5.8 for input and output requirements.
(5) The voltage on DVIO is not supervised or monitored.
(6) When in crystal bypass mode, XIN can be configured so that it can support an input digital waveform with swing levels from DVSS to DVCC or DVSS to DVIO. In this case, it is required that the pin be configured properly for the intended input swing.
(7) When in crystal bypass mode, XT2IN can be configured so that it can support an input digital waveform with swing levels from DVSS to DVCC or DVSS to DVIO. In this case, it is required that the pin be configured properly for the intended input swing.
(8) See Section 6.5 and Section 6.6 for use with BSL and JTAG functions.
(9) See Section 6.6 for use with JTAG function.
(10) This pin is configurable as reset or NMI and resides on the DVIO supply domain. When driven from external, input swing levels from DVSS to DVIO are required.
(11) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(12) This nonconfigurable reset resides on the DVCC supply domain and has an internal pullup to DVCC. When driven from external, input swing levels from DVSS to DVCC are required. This reset must be used for Spy-Bi-Wire communication and is not the same RST/NMI reset as found on other devices in the MSP430 family. See Section 6.5 and Section 6.6 for details regarding the use of this pin.