SLAS677G September   2010  – May 2020 MSP430F5304 , MSP430F5308 , MSP430F5309 , MSP430F5310

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
    8. 5.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
    10. 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    11. 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    12. 5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Crystal Oscillator, XT1, Low-Frequency Mode
    15. 5.15 Crystal Oscillator, XT2
    16. 5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    17. 5.17 Internal Reference, Low-Frequency Oscillator (REFO)
    18. 5.18 DCO Frequency
    19. 5.19 PMM, Brownout Reset (BOR)
    20. 5.20 PMM, Core Voltage
    21. 5.21 PMM, SVS High Side
    22. 5.22 PMM, SVM High Side
    23. 5.23 PMM, SVS Low Side
    24. 5.24 PMM, SVM Low Side
    25. 5.25 Wake-up Times From Low-Power Modes and Reset
    26. 5.26 Timer_A
    27. 5.27 Timer_B
    28. 5.28 USCI (UART Mode) Clock Frequency
    29. 5.29 USCI (UART Mode)
    30. 5.30 USCI (SPI Master Mode) Clock Frequency
    31. 5.31 USCI (SPI Master Mode)
    32. 5.32 USCI (SPI Slave Mode)
    33. 5.33 USCI (I2C Mode)
    34. 5.34 10-Bit ADC, Power Supply and Input Range Conditions
    35. 5.35 10-Bit ADC, Timing Parameters
    36. 5.36 10-Bit ADC, Linearity Parameters
    37. 5.37 REF, External Reference
    38. 5.38 REF, Built-In Reference
    39. 5.39 Comparator_B
    40. 5.40 Ports PU.0 and PU.1
    41. 5.41 LDO-PWR (LDO Power System)
    42. 5.42 Flash Memory
    43. 5.43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU (Link to User's Guide)
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory (Link to User's Guide)
    8. 6.8  RAM (Link to User's Guide)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O (Link to User's Guide)
      2. 6.9.2  Port Mapping Controller (Link to User's Guide)
      3. 6.9.3  Oscillator and System Clock (Link to User's Guide)
      4. 6.9.4  Power-Management Module (PMM) (Link to User's Guide)
      5. 6.9.5  Hardware Multiplier (Link to User's Guide)
      6. 6.9.6  Real-Time Clock (RTC_A) (Link to User's Guide)
      7. 6.9.7  Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.9.8  System Module (SYS) (Link to User's Guide)
      9. 6.9.9  DMA Controller (Link to User's Guide)
      10. 6.9.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.9.11 TA0 (Link to User's Guide)
      12. 6.9.12 TA1 (Link to User's Guide)
      13. 6.9.13 TA2 (Link to User's Guide)
      14. 6.9.14 TB0 (Link to User's Guide)
      15. 6.9.15 Comparator_B (Link to User's Guide)
      16. 6.9.16 ADC10_A (Link to User's Guide)
      17. 6.9.17 CRC16 (Link to User's Guide)
      18. 6.9.18 Reference (REF) Module Voltage Reference (Link to User's Guide)
      19. 6.9.19 LDO and Port U
      20. 6.9.20 Embedded Emulation Module (EEM) (S Version) (Link to User's Guide)
    10. 6.10 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.11.6  Port P5 (P5.2) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P5 (P5.3) Input/Output With Schmitt Trigger
      8. 6.11.8  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      9. 6.11.9  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      10. 6.11.10 Port U (PU.0 and PU.1) Input/Output
      11. 6.11.11 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      12. 6.11.12 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    12. 6.12 Device Descriptors
  7. 7Device and Documentation Support
    1. 7.1 Getting Started and Next Steps
    2. 7.2 Device Nomenclature
    3. 7.3 Tools and Software
    4. 7.4 Documentation Support
    5. 7.5 Related Links
    6. 7.6 Community Resources
    7. 7.7 Trademarks
    8. 7.8 Electrostatic Discharge Caution
    9. 7.9 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9.2 Port Mapping Controller (Link to User's Guide)

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4 (see Table 6-6). Table 6-7 lists the default settings for all pins that support port mapping.

Table 6-6 Port Mapping Mnemonics and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
1 PM_CBOUT0 – Comparator_B output
PM_TB0CLK TB0 clock input –
2 PM_ADC10CLK – ADC10CLK
PM_DMAE0 DMAE0 input –
3 PM_SVMOUT – SVM output
PM_TB0OUTH TB0 high impedance input TB0OUTH –
4 PM_TB0CCR0A TB0 CCR0 capture input CCI0A TB0 CCR0 compare output Out0
5 PM_TB0CCR1A TB0 CCR1 capture input CCI1A TB0 CCR1 compare output Out1
6 PM_TB0CCR2A TB0 CCR2 capture input CCI2A TB0 CCR2 compare output Out2
7 PM_TB0CCR3A TB0 CCR3 capture input CCI3A TB0 CCR3 compare output Out3
8 PM_TB0CCR4A TB0 CCR4 capture input CCI4A TB0 CCR4 compare output Out4
9 PM_TB0CCR5A TB0 CCR5 capture input CCI5A TB0 CCR5 compare output Out5
10 PM_TB0CCR6A TB0 CCR6 capture input CCI6A TB0 CCR6 compare output Out6
11 PM_UCA1RXD USCI_A1 UART RXD (Direction controlled by USCI – input)
PM_UCA1SOMI USCI_A1 SPI slave out master in (direction controlled by USCI)
12 PM_UCA1TXD USCI_A1 UART TXD (Direction controlled by USCI – output)
PM_UCA1SIMO USCI_A1 SPI slave in master out (direction controlled by USCI)
13 PM_UCA1CLK USCI_A1 clock input/output (direction controlled by USCI)
PM_UCB1STE USCI_B1 SPI slave transmit enable (direction controlled by USCI)
14 PM_UCB1SOMI USCI_B1 SPI slave out master in (direction controlled by USCI)
PM_UCB1SCL USCI_B1 I2C clock (open drain and direction controlled by USCI)
15 PM_UCB1SIMO USCI_B1 SPI slave in master out (direction controlled by USCI)
PM_UCB1SDA USCI_B1 I2C data (open drain and direction controlled by USCI)
16 PM_UCB1CLK USCI_B1 clock input/output (direction controlled by USCI)
PM_UCA1STE USCI_A1 SPI slave transmit enable (direction controlled by USCI)
17 PM_CBOUT1 None Comparator_B output
18 PM_MCLK None MCLK
19 PM_RTCCLK None RTCCLK output
20 PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI – input)
PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)
21 PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI – output)
PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
22 PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI)
23 PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
24 PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
25 PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI)
26-30 Reserved None DVSS
31 (0FFh)(1) PM_ANALOG Disables the output driver as well as the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are 5 bits wide, and the upper bits are ignored, which results in a read value of 31.

Table 6-7 Default Mapping

PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
P4.0/P4MAP0 PM_UCB1STE/PM_UCA1CLK USCI_B1 SPI slave transmit enable (direction controlled by USCI)
USCI_A1 clock input/output (direction controlled by USCI)
P4.1/P4MAP1 PM_UCB1SIMO/PM_UCB1SDA USCI_B1 SPI slave in master out (direction controlled by USCI)
USCI_B1 I2C data (open drain and direction controlled by USCI)
P4.2/P4MAP2 PM_UCB1SOMI/PM_UCB1SCL USCI_B1 SPI slave out master in (direction controlled by USCI)
USCI_B1 I2C clock (open drain and direction controlled by USCI)
P4.3/P4MAP3 PM_UCB1CLK/PM_UCA1STE USCI_A1 SPI slave transmit enable (direction controlled by USCI)
USCI_B1 clock input/output (direction controlled by USCI)
P4.4/P4MAP4 PM_UCA1TXD/PM_UCA1SIMO USCI_A1 UART TXD (Direction controlled by USCI – output)
USCI_A1 SPI slave in master out (direction controlled by USCI)
P4.5/P4MAP5 PM_UCA1RXD/PM_UCA1SOMI USCI_A1 UART RXD (Direction controlled by USCI – input)
USCI_A1 SPI slave out master in (direction controlled by USCI)
P4.6/P4MAP6 PM_NONE None DVSS
P4.7/P4MAP7 PM_NONE None DVSS