SLAS678G August   2010  – September 2020 MSP430F5324 , MSP430F5325 , MSP430F5326 , MSP430F5327 , MSP430F5328 , MSP430F5329

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagrams
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
    8. 8.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 8.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
    10. 8.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    11. 8.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    12. 8.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    13. 8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 8.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 8.16 Crystal Oscillator, XT2
    17. 8.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 8.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 8.19 DCO Frequency
    20. 8.20 PMM, Brownout Reset (BOR)
    21. 8.21 PMM, Core Voltage
    22. 8.22 PMM, SVS High Side
    23. 8.23 PMM, SVM High Side
    24. 8.24 PMM, SVS Low Side
    25. 8.25 PMM, SVM Low Side
    26. 8.26 Wake-up Times From Low-Power Modes and Reset
    27. 8.27 Timer_A
    28. 8.28 Timer_B
    29. 8.29 USCI (UART Mode) Clock Frequency
    30. 8.30 USCI (UART Mode)
    31. 8.31 USCI (SPI Master Mode) Clock Frequency
    32. 8.32 USCI (SPI Master Mode)
    33. 8.33 USCI (SPI Slave Mode)
    34. 8.34 USCI (I2C Mode)
    35. 8.35 12-Bit ADC, Power Supply and Input Range Conditions
    36. 8.36 12-Bit ADC, Timing Parameters
    37. 8.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    38. 8.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 8.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 8.40 REF, External Reference
    41. 8.41 REF, Built-In Reference
    42. 8.42 Comparator B
    43. 8.43 Ports PU.0 and PU.1
    44. 8.44 LDO-PWR (LDO Power System)
    45. 8.45 Flash Memory
    46. 8.46 JTAG and Spy-Bi-Wire Interface
  9. Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Memory Organization
    5. 9.5  Bootloader (BSL)
    6. 9.6  JTAG Operation
      1. 9.6.1 JTAG Standard Interface
      2. 9.6.2 Spy-Bi-Wire Interface
    7. 9.7  Flash Memory
    8. 9.8  RAM
    9. 9.9  Peripherals
      1. 9.9.1  Digital I/O
      2. 9.9.2  Port Mapping Controller
      3. 9.9.3  Oscillator and System Clock
      4. 9.9.4  Power-Management Module (PMM)
      5. 9.9.5  Hardware Multiplier (MPY)
      6. 9.9.6  Real-Time Clock (RTC_A)
      7. 9.9.7  Watchdog Timer (WDT_A)
      8. 9.9.8  System Module (SYS)
      9. 9.9.9  DMA Controller
      10. 9.9.10 Universal Serial Communication Interface (USCI)
      11. 9.9.11 TA0
      12. 9.9.12 TA1
      13. 9.9.13 TA2
      14. 9.9.14 TB0
      15. 9.9.15 Comparator_B
      16. 9.9.16 ADC12_A
      17. 9.9.17 CRC16
      18. 9.9.18 REF Voltage Reference
      19. 9.9.19 Embedded Emulation Module (EEM)
      20. 9.9.20 Peripheral File Map
    10. 9.10 Input/Output Diagrams
      1. 9.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.10.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.10.6  Port P5 (P5.2) Input/Output With Schmitt Trigger
      7. 9.10.7  Port P5 (P5.3) Input/Output With Schmitt Trigger
      8. 9.10.8  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      9. 9.10.9  Port P5 (P5.6 to P5.7), Input/Output With Schmitt Trigger
      10. 9.10.10 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      11. 9.10.11 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      12. 9.10.12 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      13. 9.10.13 Port P8 (P8.0 to P8.2) Input/Output With Schmitt Trigger
      14. 9.10.14 Port U (PU.0 and PU.1)
      15. 9.10.15 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      16. 9.10.16 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 9.11 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  Support Resources
    7. 10.7  Trademarks
    8. 10.8  Electrostatic Discharge Caution
    9. 10.9  Export Control Notice
    10. 10.10 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 9-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 9-1 Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCEINTERRUPT FLAGSYSTEM INTERRUPTWORD ADDRESSPRIORITY
System Reset
Power up
External reset
Watchdog time-out, password violation
Flash memory password violation
PMM password violation
WDTIFG, KEYV (SYSRSTIV)(1) (3)Reset0FFFEh63, highest
System NMI
PMM
Vacant memory access
JTAG mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBINIFG, JMBOUTIFG (SYSSNIV)(1)(Non)maskable0FFFCh62
User NMI
NMI
Oscillator fault
Flash memory access violation
NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)(1) (3)(Non)maskable0FFFAh61
Comp_BComparator B interrupt flags (CBIV)(1) (2)Maskable0FFF8h60
TB0TB0CCR0 CCIFG0 (2)Maskable0FFF6h59
TB0TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV)(1) (2)
Maskable0FFF4h58
Watchdog Timer_A interval timer modeWDTIFGMaskable0FFF2h57
USCI_A0 receive or transmitUCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (2)Maskable0FFF0h56
USCI_B0 receive or transmitUCB0RXIFG, UCB0TXIFG (UCB0IV)(1) (2)Maskable0FFEEh55
ADC12_AADC12IFG0 to ADC12IFG15 (ADC12IV)(1) (2) (5)Maskable0FFECh54
TA0TA0CCR0 CCIFG0(2)Maskable0FFEAh53
TA0TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1) (2)
Maskable0FFE8h52
LDO-PWRLDOOFFIG, LDOONIFG, LDOOVLIFGMaskable0FFE6h51
DMADMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) (2)Maskable0FFE4h50
TA1TA1CCR0 CCIFG0(2)Maskable0FFE2h49
TA1TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1) (2)
Maskable0FFE0h48
I/O port P1P1IFG.0 to P1IFG.7 (P1IV)(1) (2)Maskable0FFDEh47
USCI_A1 receive or transmitUCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (2)Maskable0FFDCh46
USCI_B1 receive or transmitUCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (2)Maskable0FFDAh45
TA2TA2CCR0 CCIFG0(2)Maskable0FFD8h44
TA2TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV)(1) (2)
Maskable0FFD6h43
I/O port P2P2IFG.0 to P2IFG.7 (P2IV)(1) (2)Maskable0FFD4h42
RTC_ARTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV)(1) (2)Maskable0FFD2h41
ReservedReserved(4)0FFD0h40
0FF80h0, lowest
Multiple source flags
Interrupt flags are in the module.
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations.
Only on devices with ADC, otherwise reserved.