SLAS678G August   2010  – September 2020 MSP430F5324 , MSP430F5325 , MSP430F5326 , MSP430F5327 , MSP430F5328 , MSP430F5329

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
    8. 8.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 8.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
    10. 8.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    11. 8.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    12. 8.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    13. 8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 8.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 8.16 Crystal Oscillator, XT2
    17. 8.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 8.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 8.19 DCO Frequency
    20. 8.20 PMM, Brownout Reset (BOR)
    21. 8.21 PMM, Core Voltage
    22. 8.22 PMM, SVS High Side
    23. 8.23 PMM, SVM High Side
    24. 8.24 PMM, SVS Low Side
    25. 8.25 PMM, SVM Low Side
    26. 8.26 Wake-up Times From Low-Power Modes and Reset
    27. 8.27 Timer_A
    28. 8.28 Timer_B
    29. 8.29 USCI (UART Mode) Clock Frequency
    30. 8.30 USCI (UART Mode)
    31. 8.31 USCI (SPI Master Mode) Clock Frequency
    32. 8.32 USCI (SPI Master Mode)
    33. 8.33 USCI (SPI Slave Mode)
    34. 8.34 USCI (I2C Mode)
    35. 8.35 12-Bit ADC, Power Supply and Input Range Conditions
    36. 8.36 12-Bit ADC, Timing Parameters
    37. 8.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    38. 8.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 8.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 8.40 REF, External Reference
    41. 8.41 REF, Built-In Reference
    42. 8.42 Comparator B
    43. 8.43 Ports PU.0 and PU.1
    44. 8.44 LDO-PWR (LDO Power System)
    45. 8.45 Flash Memory
    46. 8.46 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Memory Organization
    5. 9.5  Bootloader (BSL)
    6. 9.6  JTAG Operation
      1. 9.6.1 JTAG Standard Interface
      2. 9.6.2 Spy-Bi-Wire Interface
    7. 9.7  Flash Memory
    8. 9.8  RAM
    9. 9.9  Peripherals
      1. 9.9.1  Digital I/O
      2. 9.9.2  Port Mapping Controller
      3. 9.9.3  Oscillator and System Clock
      4. 9.9.4  Power-Management Module (PMM)
      5. 9.9.5  Hardware Multiplier (MPY)
      6. 9.9.6  Real-Time Clock (RTC_A)
      7. 9.9.7  Watchdog Timer (WDT_A)
      8. 9.9.8  System Module (SYS)
      9. 9.9.9  DMA Controller
      10. 9.9.10 Universal Serial Communication Interface (USCI)
      11. 9.9.11 TA0
      12. 9.9.12 TA1
      13. 9.9.13 TA2
      14. 9.9.14 TB0
      15. 9.9.15 Comparator_B
      16. 9.9.16 ADC12_A
      17. 9.9.17 CRC16
      18. 9.9.18 REF Voltage Reference
      19. 9.9.19 Embedded Emulation Module (EEM)
      20. 9.9.20 Peripheral File Map
    10. 9.10 Input/Output Diagrams
      1. 9.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.10.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.10.6  Port P5 (P5.2) Input/Output With Schmitt Trigger
      7. 9.10.7  Port P5 (P5.3) Input/Output With Schmitt Trigger
      8. 9.10.8  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      9. 9.10.9  Port P5 (P5.6 to P5.7), Input/Output With Schmitt Trigger
      10. 9.10.10 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      11. 9.10.11 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      12. 9.10.12 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      13. 9.10.13 Port P8 (P8.0 to P8.2) Input/Output With Schmitt Trigger
      14. 9.10.14 Port U (PU.0 and PU.1)
      15. 9.10.15 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      16. 9.10.16 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 9.11 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  Support Resources
    7. 10.7  Trademarks
    8. 10.8  Electrostatic Discharge Caution
    9. 10.9  Export Control Notice
    10. 10.10 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.9.20 Peripheral File Map

Table 9-14 lists the base address and offset range for each module. Table 9-15 through Table 9-43 list all of the available registers for each module.

Table 9-14 Peripherals
MODULE NAMEBASE ADDRESSOFFSET ADDRESS RANGE
Special Functions (see Table 9-15)0100h000h to 01Fh
PMM (see Table 9-16)0120h000h to 010h
Flash Control (see Table 9-17)0140h000h to 00Fh
CRC16 (see Table 9-18)0150h000h to 007h
RAM Control (see Table 9-19)0158h000h to 001h
Watchdog (see Table 9-20)015Ch000h to 001h
UCS (see Table 9-21)0160h000h to 01Fh
SYS (see Table 9-22)0180h000h to 01Fh
Shared Reference (see Table 9-23)01B0h000h to 001h
Port Mapping Control (see Table 9-24)01C0h000h to 002h
Port Mapping Port P4 (see Table 9-24)01E0h000h to 007h
Port P1, P2 (see Table 9-25)0200h000h to 01Fh
Port P3, P4 (see Table 9-26)0220h000h to 00Bh
Port P5, P6 (see Table 9-27)0240h000h to 00Bh
Port P7, P8 (see Table 9-28)0260h000h to 00Bh
Port PJ (see Table 9-29)0320h000h to 01Fh
TA0 (see Table 9-30)0340h000h to 02Eh
TA1 (see Table 9-31)0380h000h to 02Eh
TB0 (see Table 9-32)03C0h000h to 02Eh
TA2 (see Table 9-33)0400h000h to 02Eh
Real-Time Clock (RTC_A) (see Table 9-34)04A0h000h to 01Bh
32-Bit Hardware Multiplier (see Table 9-35)04C0h000h to 02Fh
DMA General Control (see Table 9-36)0500h000h to 00Fh
DMA Channel 0 (see Table 9-36)0510h000h to 00Ah
DMA Channel 1 (see Table 9-36)0520h000h to 00Ah
DMA Channel 2 (see Table 9-36)0530h000h to 00Ah
USCI_A0 (see Table 9-37)05C0h000h to 01Fh
USCI_B0 (see Table 9-38)05E0h000h to 01Fh
USCI_A1 (see Table 9-39)0600h000h to 01Fh
USCI_B1 (see Table 9-40)0620h000h to 01Fh
ADC12_A (see Table 9-41)0700h000h to 03Eh
Comparator_B (see Table 9-42)08C0h000h to 00Fh
LDO-PWR and Port U configuration (see Table 9-43)0900h000h to 014h
Table 9-15 Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTIONREGISTEROFFSET
SFR interrupt enableSFRIE100h
SFR interrupt flagSFRIFG102h
SFR reset pin controlSFRRPCR04h
Table 9-16 PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTIONREGISTEROFFSET
PMM control 0PMMCTL000h
PMM control 1PMMCTL102h
SVS high-side controlSVSMHCTL04h
SVS low-side controlSVSMLCTL06h
PMM interrupt flagsPMMIFG0Ch
PMM interrupt enablePMMIE0Eh
PMM power mode 5 controlPM5CTL010h
Table 9-17 Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTIONREGISTEROFFSET
Flash control 1FCTL100h
Flash control 3FCTL304h
Flash control 4FCTL406h
Table 9-18 CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTIONREGISTEROFFSET
CRC data inputCRC16DI00h
CRC data input reverse byteCRCDIRB02h
CRC initialization and resultCRCINIRES04h
CRC result reverse byteCRCRESR06h
Table 9-19 RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTIONREGISTEROFFSET
RAM control 0RCCTL000h
Table 9-20 Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTIONREGISTEROFFSET
Watchdog timer controlWDTCTL00h
Table 9-21 UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTIONREGISTEROFFSET
UCS control 0UCSCTL000h
UCS control 1UCSCTL102h
UCS control 2UCSCTL204h
UCS control 3UCSCTL306h
UCS control 4UCSCTL408h
UCS control 5UCSCTL50Ah
UCS control 6UCSCTL60Ch
UCS control 7UCSCTL70Eh
UCS control 8UCSCTL810h
Table 9-22 SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTIONREGISTEROFFSET
System controlSYSCTL00h
Bootloader configuration areaSYSBSLC02h
JTAG mailbox controlSYSJMBC06h
JTAG mailbox input 0SYSJMBI008h
JTAG mailbox input 1SYSJMBI10Ah
JTAG mailbox output 0SYSJMBO00Ch
JTAG mailbox output 1SYSJMBO10Eh
Bus error vector generatorSYSBERRIV18h
User NMI vector generatorSYSUNIV1Ah
System NMI vector generatorSYSSNIV1Ch
Reset vector generatorSYSRSTIV1Eh
Table 9-23 Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTIONREGISTEROFFSET
Shared reference controlREFCTL00h
Table 9-24 Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h)
REGISTER DESCRIPTIONREGISTEROFFSET
Port mapping key/IDPMAPKEYID00h
Port mapping controlPMAPCTL02h
Port P4.0 mappingP4MAP000h
Port P4.1 mappingP4MAP101h
Port P4.2 mappingP4MAP202h
Port P4.3 mappingP4MAP303h
Port P4.4 mappingP4MAP404h
Port P4.5 mappingP4MAP505h
Port P4.6 mappingP4MAP606h
Port P4.7 mappingP4MAP707h
Table 9-25 Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTIONREGISTEROFFSET
Port P1 inputP1IN00h
Port P1 outputP1OUT02h
Port P1 directionP1DIR04h
Port P1 resistor enableP1REN06h
Port P1 drive strengthP1DS08h
Port P1 selectionP1SEL0Ah
Port P1 interrupt vector wordP1IV0Eh
Port P1 interrupt edge selectP1IES18h
Port P1 interrupt enableP1IE1Ah
Port P1 interrupt flagP1IFG1Ch
Port P2 inputP2IN01h
Port P2 outputP2OUT03h
Port P2 directionP2DIR05h
Port P2 resistor enableP2REN07h
Port P2 drive strengthP2DS09h
Port P2 selectionP2SEL0Bh
Port P2 interrupt vector wordP2IV1Eh
Port P2 interrupt edge selectP2IES19h
Port P2 interrupt enableP2IE1Bh
Port P2 interrupt flagP2IFG1Dh
Table 9-26 Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTIONREGISTEROFFSET
Port P3 inputP3IN00h
Port P3 outputP3OUT02h
Port P3 directionP3DIR04h
Port P3 resistor enableP3REN06h
Port P3 drive strengthP3DS08h
Port P3 selectionP3SEL0Ah
Port P4 inputP4IN01h
Port P4 outputP4OUT03h
Port P4 directionP4DIR05h
Port P4 resistor enableP4REN07h
Port P4 drive strengthP4DS09h
Port P4 selectionP4SEL0Bh
Table 9-27 Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTIONREGISTEROFFSET
Port P5 inputP5IN00h
Port P5 outputP5OUT02h
Port P5 directionP5DIR04h
Port P5 resistor enableP5REN06h
Port P5 drive strengthP5DS08h
Port P5 selectionP5SEL0Ah
Port P6 inputP6IN01h
Port P6 outputP6OUT03h
Port P6 directionP6DIR05h
Port P6 resistor enableP6REN07h
Port P6 drive strengthP6DS09h
Port P6 selectionP6SEL0Bh
Table 9-28 Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTIONREGISTEROFFSET
Port P7 inputP7IN00h
Port P7 outputP7OUT02h
Port P7 directionP7DIR04h
Port P7 resistor enableP7REN06h
Port P7 drive strengthP7DS08h
Port P7 selectionP7SEL0Ah
Port P8 inputP8IN01h
Port P8 outputP8OUT03h
Port P8 directionP8DIR05h
Port P8 resistor enableP8REN07h
Port P8 drive strengthP8DS09h
Port P8 selectionP8SEL0Bh
Table 9-29 Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTIONREGISTEROFFSET
Port PJ inputPJIN00h
Port PJ outputPJOUT02h
Port PJ directionPJDIR04h
Port PJ resistor enablePJREN06h
Port PJ drive strengthPJDS08h
Table 9-30 TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTIONREGISTEROFFSET
TA0 controlTA0CTL00h
Capture/compare control 0TA0CCTL002h
Capture/compare control 1TA0CCTL104h
Capture/compare control 2TA0CCTL206h
Capture/compare control 3TA0CCTL308h
Capture/compare control 4TA0CCTL40Ah
TA0 counterTA0R10h
Capture/compare 0TA0CCR012h
Capture/compare 1TA0CCR114h
Capture/compare 2TA0CCR216h
Capture/compare 3TA0CCR318h
Capture/compare 4TA0CCR41Ah
TA0 expansion 0TA0EX020h
TA0 interrupt vectorTA0IV2Eh
Table 9-31 TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTIONREGISTEROFFSET
TA1 controlTA1CTL00h
Capture/compare control 0TA1CCTL002h
Capture/compare control 1TA1CCTL104h
Capture/compare control 2TA1CCTL206h
TA1 counterTA1R10h
Capture/compare 0TA1CCR012h
Capture/compare 1TA1CCR114h
Capture/compare 2TA1CCR216h
TA1 expansion 0TA1EX020h
TA1 interrupt vectorTA1IV2Eh
Table 9-32 TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTIONREGISTEROFFSET
TB0 controlTB0CTL00h
Capture/compare control 0TB0CCTL002h
Capture/compare control 1TB0CCTL104h
Capture/compare control 2TB0CCTL206h
Capture/compare control 3TB0CCTL308h
Capture/compare control 4TB0CCTL40Ah
Capture/compare control 5TB0CCTL50Ch
Capture/compare control 6TB0CCTL60Eh
TB0 counterTB0R10h
Capture/compare 0TB0CCR012h
Capture/compare 1TB0CCR114h
Capture/compare 2TB0CCR216h
Capture/compare 3TB0CCR318h
Capture/compare 4TB0CCR41Ah
Capture/compare 5TB0CCR51Ch
Capture/compare 6TB0CCR61Eh
TB0 expansion 0TB0EX020h
TB0 interrupt vectorTB0IV2Eh
Table 9-33 TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTIONREGISTEROFFSET
TA2 controlTA2CTL00h
Capture/compare control 0TA2CCTL002h
Capture/compare control 1TA2CCTL104h
Capture/compare control 2TA2CCTL206h
TA2 counterTA2R10h
Capture/compare 0TA2CCR012h
Capture/compare 1TA2CCR114h
Capture/compare 2TA2CCR216h
TA2 expansion 0TA2EX020h
TA2 interrupt vectorTA2IV2Eh
Table 9-34 Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTIONREGISTEROFFSET
RTC control 0RTCCTL000h
RTC control 1RTCCTL101h
RTC control 2RTCCTL202h
RTC control 3RTCCTL303h
RTC prescaler 0 controlRTCPS0CTL08h
RTC prescaler 1 controlRTCPS1CTL0Ah
RTC prescaler 0RTCPS00Ch
RTC prescaler 1RTCPS10Dh
RTC interrupt vector wordRTCIV0Eh
RTC seconds/counter 1RTCSEC/RTCNT110h
RTC minutes/counter 2RTCMIN/RTCNT211h
RTC hours/counter 3RTCHOUR/RTCNT312h
RTC day of week/counter 4RTCDOW/RTCNT413h
RTC daysRTCDAY14h
RTC monthRTCMON15h
RTC year lowRTCYEARL16h
RTC year highRTCYEARH17h
RTC alarm minutesRTCAMIN18h
RTC alarm hoursRTCAHOUR19h
RTC alarm day of weekRTCADOW1Ah
RTC alarm dayRTCADAY1Bh
Table 9-35 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTIONREGISTEROFFSET
16-bit operand 1 – multiplyMPY00h
16-bit operand 1 – signed multiplyMPYS02h
16-bit operand 1 – multiply accumulateMAC04h
16-bit operand 1 – signed multiply accumulateMACS06h
16-bit operand 2OP208h
16 × 16 result low wordRESLO0Ah
16 × 16 result high wordRESHI0Ch
16 × 16 sum extensionSUMEXT0Eh
32-bit operand 1 – multiply low wordMPY32L10h
32-bit operand 1 – multiply high wordMPY32H12h
32-bit operand 1 – signed multiply low wordMPYS32L14h
32-bit operand 1 – signed multiply high wordMPYS32H16h
32-bit operand 1 – multiply accumulate low wordMAC32L18h
32-bit operand 1 – multiply accumulate high wordMAC32H1Ah
32-bit operand 1 – signed multiply accumulate low wordMACS32L1Ch
32-bit operand 1 – signed multiply accumulate high wordMACS32H1Eh
32-bit operand 2 – low wordOP2L20h
32-bit operand 2 – high wordOP2H22h
32 × 32 result 0 – least significant wordRES024h
32 × 32 result 1RES126h
32 × 32 result 2RES228h
32 × 32 result 3 – most significant wordRES32Ah
MPY32 control 0MPY32CTL02Ch
Table 9-36 DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTIONREGISTEROFFSET
DMA channel 0 controlDMA0CTL00h
DMA channel 0 source address lowDMA0SAL02h
DMA channel 0 source address highDMA0SAH04h
DMA channel 0 destination address lowDMA0DAL06h
DMA channel 0 destination address highDMA0DAH08h
DMA channel 0 transfer sizeDMA0SZ0Ah
DMA channel 1 controlDMA1CTL00h
DMA channel 1 source address lowDMA1SAL02h
DMA channel 1 source address highDMA1SAH04h
DMA channel 1 destination address lowDMA1DAL06h
DMA channel 1 destination address highDMA1DAH08h
DMA channel 1 transfer sizeDMA1SZ0Ah
DMA channel 2 controlDMA2CTL00h
DMA channel 2 source address lowDMA2SAL02h
DMA channel 2 source address highDMA2SAH04h
DMA channel 2 destination address lowDMA2DAL06h
DMA channel 2 destination address highDMA2DAH08h
DMA channel 2 transfer sizeDMA2SZ0Ah
DMA module control 0DMACTL000h
DMA module control 1DMACTL102h
DMA module control 2DMACTL204h
DMA module control 3DMACTL306h
DMA module control 4DMACTL408h
DMA interrupt vectorDMAIV0Eh
Table 9-37 USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTIONREGISTEROFFSET
USCI control 1UCA0CTL100h
USCI control 0UCA0CTL001h
USCI baud rate 0UCA0BR006h
USCI baud rate 1UCA0BR107h
USCI modulation controlUCA0MCTL08h
USCI statusUCA0STAT0Ah
USCI receive bufferUCA0RXBUF0Ch
USCI transmit bufferUCA0TXBUF0Eh
USCI LIN controlUCA0ABCTL10h
USCI IrDA transmit controlUCA0IRTCTL12h
USCI IrDA receive controlUCA0IRRCTL13h
USCI interrupt enableUCA0IE1Ch
USCI interrupt flagsUCA0IFG1Dh
USCI interrupt vector wordUCA0IV1Eh
Table 9-38 USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTIONREGISTEROFFSET
USCI synchronous control 1UCB0CTL100h
USCI synchronous control 0UCB0CTL001h
USCI synchronous bit rate 0UCB0BR006h
USCI synchronous bit rate 1UCB0BR107h
USCI synchronous statusUCB0STAT0Ah
USCI synchronous receive bufferUCB0RXBUF0Ch
USCI synchronous transmit bufferUCB0TXBUF0Eh
USCI I2C own addressUCB0I2COA10h
USCI I2C slave addressUCB0I2CSA12h
USCI interrupt enableUCB0IE1Ch
USCI interrupt flagsUCB0IFG1Dh
USCI interrupt vector wordUCB0IV1Eh
Table 9-39 USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTIONREGISTEROFFSET
USCI control 1UCA1CTL100h
USCI control 0UCA1CTL001h
USCI baud rate 0UCA1BR006h
USCI baud rate 1UCA1BR107h
USCI modulation controlUCA1MCTL08h
USCI statusUCA1STAT0Ah
USCI receive bufferUCA1RXBUF0Ch
USCI transmit bufferUCA1TXBUF0Eh
USCI LIN controlUCA1ABCTL10h
USCI IrDA transmit controlUCA1IRTCTL12h
USCI IrDA receive controlUCA1IRRCTL13h
USCI interrupt enableUCA1IE1Ch
USCI interrupt flagsUCA1IFG1Dh
USCI interrupt vector wordUCA1IV1Eh
Table 9-40 USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTIONREGISTEROFFSET
USCI synchronous control 1UCB1CTL100h
USCI synchronous control 0UCB1CTL001h
USCI synchronous bit rate 0UCB1BR006h
USCI synchronous bit rate 1UCB1BR107h
USCI synchronous statusUCB1STAT0Ah
USCI synchronous receive bufferUCB1RXBUF0Ch
USCI synchronous transmit bufferUCB1TXBUF0Eh
USCI I2C own addressUCB1I2COA10h
USCI I2C slave addressUCB1I2CSA12h
USCI interrupt enableUCB1IE1Ch
USCI interrupt flagsUCB1IFG1Dh
USCI interrupt vector wordUCB1IV1Eh
Table 9-41 ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTIONREGISTEROFFSET
ADC control 0ADC12CTL000h
ADC control 1ADC12CTL102h
ADC control 2ADC12CTL204h
ADC interrupt flagADC12IFG0Ah
ADC interrupt enableADC12IE0Ch
ADC interrupt vector wordADC12IV0Eh
ADC memory control 0ADC12MCTL010h
ADC memory control 1ADC12MCTL111h
ADC memory control 2ADC12MCTL212h
ADC memory control 3ADC12MCTL313h
ADC memory control 4ADC12MCTL414h
ADC memory control 5ADC12MCTL515h
ADC memory control 6ADC12MCTL616h
ADC memory control 7ADC12MCTL717h
ADC memory control 8ADC12MCTL818h
ADC memory control 9ADC12MCTL919h
ADC memory control 10ADC12MCTL101Ah
ADC memory control 11ADC12MCTL111Bh
ADC memory control 12ADC12MCTL121Ch
ADC memory control 13ADC12MCTL131Dh
ADC memory control 14ADC12MCTL141Eh
ADC memory control 15ADC12MCTL151Fh
Conversion memory 0ADC12MEM020h
Conversion memory 1ADC12MEM122h
Conversion memory 2ADC12MEM224h
Conversion memory 3ADC12MEM326h
Conversion memory 4ADC12MEM428h
Conversion memory 5ADC12MEM52Ah
Conversion memory 6ADC12MEM62Ch
Conversion memory 7ADC12MEM72Eh
Conversion memory 8ADC12MEM830h
Conversion memory 9ADC12MEM932h
Conversion memory 10ADC12MEM1034h
Conversion memory 11ADC12MEM1136h
Conversion memory 12ADC12MEM1238h
Conversion memory 13ADC12MEM133Ah
Conversion memory 14ADC12MEM143Ch
Conversion memory 15ADC12MEM153Eh
Table 9-42 Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTIONREGISTEROFFSET
Comp_B control 0CBCTL000h
Comp_B control 1CBCTL102h
Comp_B control 2CBCTL204h
Comp_B control 3CBCTL306h
Comp_B interruptCBINT0Ch
Comp_B interrupt vector wordCBIV0Eh
Table 9-43 LDO and Port U Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTIONREGISTEROFFSET
LDO key/IDLDOKEYPID00h
PU port controlPUCTL04h
LDO power controlLDOPWRCTL08h