SLAS655H January   2010  – May 2021 MSP430F5418A , MSP430F5419A , MSP430F5435A , MSP430F5436A , MSP430F5437A , MSP430F5438A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O
    8. 8.8  Inputs – Ports P1 and P2
    9. 8.9  Leakage Current – General-Purpose I/O
    10. 8.10 Outputs – General-Purpose I/O (Full Drive Strength)
    11. 8.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
    12. 8.12 Output Frequency – General-Purpose I/O
    13. 8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 8.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 8.16 Crystal Oscillator, XT1, High-Frequency Mode
    17. 8.17 Crystal Oscillator, XT2
    18. 8.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 8.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 8.20 DCO Frequency
    21. 8.21 PMM, Brownout Reset (BOR)
    22. 8.22 PMM, Core Voltage
    23. 8.23 PMM, SVS High Side
    24. 8.24 PMM, SVM High Side
    25. 8.25 PMM, SVS Low Side
    26. 8.26 PMM, SVM Low Side
    27. 8.27 Wake-up Times From Low-Power Modes and Reset
    28. 8.28 Timer_A
    29. 8.29 Timer_B
    30. 8.30 USCI (UART Mode) Clock Frequency
    31. 8.31 USCI (UART Mode)
    32. 8.32 USCI (SPI Master Mode) Clock Frequency
    33. 8.33 USCI (SPI Master Mode)
    34. 8.34 USCI (SPI Slave Mode)
    35. 8.35 USCI (I2C Mode)
    36. 8.36 12-Bit ADC, Power Supply and Input Range Conditions
    37. 8.37 12-Bit ADC, Timing Parameters
    38. 8.38 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    39. 8.39 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    40. 8.40 12-Bit ADC, Temperature Sensor and Built-In VMID
    41. 8.41 REF, External Reference
    42. 8.42 REF, Built-In Reference
    43. 8.43 Flash Memory
    44. 8.44 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Memory Organization
    5. 9.5  Bootloader (BSL)
    6. 9.6  JTAG Operation
      1. 9.6.1 JTAG Standard Interface
      2. 9.6.2 Spy-Bi-Wire Interface
    7. 9.7  Flash Memory
    8. 9.8  RAM
    9. 9.9  Peripherals
      1. 9.9.1  Digital I/O
      2. 9.9.2  Oscillator and System Clock
      3. 9.9.3  Power-Management Module (PMM)
      4. 9.9.4  Hardware Multiplier (MPY)
      5. 9.9.5  Real-Time Clock (RTC_A)
      6. 9.9.6  Watchdog Timer (WDT_A)
      7. 9.9.7  System Module (SYS)
      8. 9.9.8  DMA Controller
      9. 9.9.9  Universal Serial Communication Interface (USCI)
      10. 9.9.10 TA0
      11. 9.9.11 TA1
      12. 9.9.12 TB0
      13. 9.9.13 ADC12_A
      14. 9.9.14 CRC16
      15. 9.9.15 Reference (REF) Module Voltage Reference
      16. 9.9.16 Embedded Emulation Module (EEM) (L Version)
      17. 9.9.17 Peripheral File Map
    10. 9.10 Input/Output Diagrams
      1. 9.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.10.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.10.6  Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
      7. 9.10.7  Port P5 (P5.4 to P5.7) Input/Output With Schmitt Trigger
      8. 9.10.8  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      9. 9.10.9  Port P7 (P7.0 and P7.1) Input/Output With Schmitt Trigger
      10. 9.10.10 Port P7 (P7.2 and P7.3) Input/Output With Schmitt Trigger
      11. 9.10.11 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      12. 9.10.12 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      13. 9.10.13 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      14. 9.10.14 Port P10 (P10.0 to P10.7) Input/Output With Schmitt Trigger
      15. 9.10.15 Port P11 (P11.0 to P11.2) Input/Output With Schmitt Trigger
      16. 9.10.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      17. 9.10.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 9.11 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1 Getting Started
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Export Control Notice
    9. 10.9 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.34 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-13 and Figure 8-14)
PARAMETERTEST CONDITIONSVCCMINMAXUNIT
tSTE,LEADSTE lead time, STE low to clockPMMCOREV = 01.8 V11ns
3.0 V8
PMMCOREV = 32.4 V7
3.0 V6
tSTE,LAGSTE lag time, Last clock to STE highPMMCOREV = 01.8 V3ns
3.0 V3
PMMCOREV = 32.4 V3
3.0 V3
tSTE,ACCSTE access time, STE low to SOMI data outPMMCOREV = 01.8 V66ns
3.0 V50
PMMCOREV = 32.4 V36
3.0 V30
tSTE,DISSTE disable time, STE high to SOMI high impedancePMMCOREV = 01.8 V30ns
3.0 V23
PMMCOREV = 32.4 V16
3.0 V13
tSU,SISIMO input data setup timePMMCOREV = 01.8 V5ns
3.0 V5
PMMCOREV = 32.4 V2
3.0 V2
tHD,SISIMO input data hold timePMMCOREV = 01.8 V5ns
3.0 V5
PMMCOREV = 32.4 V5
3.0 V5
tVALID,SOSOMI output data valid time(2)UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 0		1.8 V76ns
3.0 V60
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 3		2.4 V44
3.0 V40
tHD,SOSOMI output data hold time(3)CL = 20 pF, PMMCOREV = 01.8 V18ns
3.0 V12
CL = 20 pF, PMMCOREV = 32.4 V10
3.0 V8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 8-13 and Figure 8-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 8-13 and Figure 8-14.
GUID-ABFDF693-438B-41BE-B678-7CB814312E81-low.gifFigure 8-13 SPI Slave Mode, CKPH = 0
GUID-57F1C61B-3CF0-4857-9C36-94F68E7CA227-low.gifFigure 8-14 SPI Slave Mode, CKPH = 1