SLASEU5A October 2019 – February 2021 MSP430F5438A-ET
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fUSCI | USCI input clock frequency | Internal: SMCLK, ACLK, External: UCLK, Duty cycle = 50% ± 10% |
fSYSTEM | MHz | |||
fSCL | SCL clock frequency | 2.2 V, 3 V | 0 | 400 | kHz | ||
tHD,STA | Hold time (repeated) START | fSCL ≤ 100 kHz | 2.2 V, 3 V | 4.0 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tSU,STA | Setup time for a repeated START | fSCL ≤ 100 kHz | 2.2 V, 3 V | 4.7 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tHD,DAT | Data hold time | 2.2 V, 3 V | 0 | ns | |||
tSU,DAT | Data setup time | 2.2 V, 3 V | 250 | ns | |||
tSU,STO | Setup time for STOP | fSCL ≤ 100 kHz | 2.2 V, 3 V | 4.0 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tSP | Pulse duration of spikes suppressed by input filter | 2.2 V | 50 | 600 | ns | ||
3 V | 50 | 600 |