SLAS645L July   2009  – May 2020 MSP430F5500 , MSP430F5501 , MSP430F5502 , MSP430F5503 , MSP430F5504 , MSP430F5505 , MSP430F5506 , MSP430F5507 , MSP430F5508 , MSP430F5509 , MSP430F5510

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Terminal Functions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
    8. 5.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
    10. 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    11. 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    12. 5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, XT2
    17. 5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 5.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 5.19 DCO Frequency
    20. 5.20 PMM, Brownout Reset (BOR)
    21. 5.21 PMM, Core Voltage
    22. 5.22 PMM, SVS High Side
    23. 5.23 PMM, SVM High Side
    24. 5.24 PMM, SVS Low Side
    25. 5.25 PMM, SVM Low Side
    26. 5.26 Wake-up Times From Low-Power Modes and Reset
    27. 5.27 Timer_A
    28. 5.28 Timer_B
    29. 5.29 USCI (UART Mode) Clock Frequency
    30. 5.30 USCI (UART Mode)
    31. 5.31 USCI (SPI Master Mode) Clock Frequency
    32. 5.32 USCI (SPI Master Mode)
    33. 5.33 USCI (SPI Slave Mode)
    34. 5.34 USCI (I2C Mode)
    35. 5.35 10-Bit ADC, Power Supply and Input Range Conditions
    36. 5.36 10-Bit ADC, Timing Parameters
    37. 5.37 10-Bit ADC, Linearity Parameters
    38. 5.38 REF, External Reference
    39. 5.39 REF, Built-In Reference
    40. 5.40 Comparator B
    41. 5.41 Ports PU.0 and PU.1
    42. 5.42 USB Output Ports (DP and DM)
    43. 5.43 USB Input Ports (DP and DM)
    44. 5.44 USB-PWR (USB Power System)
    45. 5.45 USB-PLL (USB Phase-Locked Loop)
    46. 5.46 Flash Memory
    47. 5.47 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU (Link to User's Guide)
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
      1. 6.5.1 USB BSL
      2. 6.5.2 UART BSL
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory (Link to User's Guide)
    8. 6.8  RAM (Link to User's Guide)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O (Link to User's Guide)
      2. 6.9.2  Port Mapping Controller (Link to User's Guide)
      3. 6.9.3  Oscillator and System Clock (Link to User's Guide)
      4. 6.9.4  Power-Management Module (PMM) (Link to User's Guide)
      5. 6.9.5  Hardware Multiplier (MPY) (Link to User's Guide)
      6. 6.9.6  Real-Time Clock (RTC_A) (Link to User's Guide)
      7. 6.9.7  Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.9.8  System Module (SYS) (Link to User's Guide)
      9. 6.9.9  DMA Controller (Link to User's Guide)
      10. 6.9.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.9.11 TA0 (Link to User's Guide)
      12. 6.9.12 TA1 (Link to User's Guide)
      13. 6.9.13 TA2 (Link to User's Guide)
      14. 6.9.14 TB0 (Link to User's Guide)
      15. 6.9.15 Comparator_B (Link to User's Guide)
      16. 6.9.16 ADC10_A (Link to User's Guide)
      17. 6.9.17 CRC16 (Link to User's Guide)
      18. 6.9.18 Reference (REF) Voltage Reference (Link to User's Guide)
      19. 6.9.19 Universal Serial Bus (USB) (Link to User's Guide)
      20. 6.9.20 Embedded Emulation Module (EEM) (S Version) (Link to User's Guide)
    10. 6.10 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.11.6  Port P5 (P5.2) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P5 (P5.3) Input/Output With Schmitt Trigger
      8. 6.11.8  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      9. 6.11.9  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      10. 6.11.10 Port U (PU.0/DP, PU.1/DM, PUR) USB Ports
      11. 6.11.11 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      12. 6.11.12 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    12. 6.12 Device Descriptors
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.35 10-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V		 1.8 3.6 V
V(Ax) Analog input voltage range(2) All ADC10_A pins: P1.0 to P1.5 and P3.6 and P3.7 terminals 0 AVCC V
IADC10_A Operating supply current into AVCC terminal, REF module and reference buffer off fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV  = 0,
ADC10SREF = 00		 2.2 V 60 100 µA
3 V 75 110
Operating supply current into AVCC terminal, REF module on, reference buffer on fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,
SHT0 = 0, SHT1 = 0, ADC10DIV  = 0,
ADC10SREF = 01		 3 V 113 150
Operating supply current into AVCC terminal, REF module off, reference buffer on fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV  = 0,
ADC10SREF = 10, VEREF = 2.5 V		 3 V 105 140
Operating supply current into AVCC terminal, REF module off, reference buffer off fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV  = 0,
ADC10SREF = 11, VEREF = 2.5 V		 3 V 70 110
CI Input capacitance Only one terminal Ax can be selected at one time from the pad to the ADC10_A capacitor array including wiring and pad. 2.2 V 3.5 pF
RI Input MUX ON resistance AVCC > 2.0 V, 0 V ≤ VAx ≤ AVCC 36 kΩ
1.8V < AVCC < 2.0 V, 0 V ≤ VAx ≤ AVCC 96
(1) The leakage current is defined in the leakage current table with P6.x/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external reference voltage requires decoupling capacitors. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430F5xx and MSP430F6xx Family User's Guide.