SLASEC3A August   2016  – August 2016 MSP430F6459-HIREL

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Schmitt-Trigger Inputs - General-Purpose I/O
    8. 5.8  Leakage Current - General-Purpose I/O
    9. 5.9  Outputs - General-Purpose I/O (Full Drive Strength)
    10. 5.10 Outputs - General-Purpose I/O (Reduced Drive Strength)
    11. 5.11 Thermal Resistance Characteristics for PZ Package
    12. 5.12 Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    13. 5.13 Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    14. 5.14 Timing and Switching Characteristics
      1. 5.14.1 Power Supply Sequencing
      2. 5.14.2 Clock Specifications
      3. 5.14.3 Peripherals
      4. 5.14.4 Emulation and Debug
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Instruction Set
    4. 6.4  Operating Modes
    5. 6.5  Interrupt Vector Addresses
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
      1. 6.7.1 UART BSL
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire Interface
    9. 6.9  Flash Memory
    10. 6.10 Memory Integrity Detection (MID)
    11. 6.11 RAM
    12. 6.12 Backup RAM
    13. 6.13 Peripherals
      1. 6.13.1  Digital I/O
      2. 6.13.2  Port Mapping Controller
      3. 6.13.3  Oscillator and System Clock
      4. 6.13.4  Power-Management Module (PMM)
      5. 6.13.5  Hardware Multiplier (MPY)
      6. 6.13.6  Real-Time Clock (RTC_B)
      7. 6.13.7  Watchdog Timer (WDT_A)
      8. 6.13.8  System Module (SYS)
      9. 6.13.9  DMA Controller
      10. 6.13.10 Universal Serial Communication Interface (USCI)
      11. 6.13.11 Timer TA0
      12. 6.13.12 Timer TA1
      13. 6.13.13 Timer TA2
      14. 6.13.14 Timer TB0
      15. 6.13.15 Comparator_B
      16. 6.13.16 ADC12_A
      17. 6.13.17 DAC12_A
      18. 6.13.18 CRC16
      19. 6.13.19 Voltage Reference (REF) Module
      20. 6.13.20 LCD_B
      21. 6.13.21 LDO and PU Port
      22. 6.13.22 Embedded Emulation Module (EEM) (L Version)
      23. 6.13.23 Peripheral File Map
    14. 6.14 Input/Output Schematics
      1. 6.14.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.14.2  Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 6.14.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
      4. 6.14.4  Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 6.14.5  Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 6.14.6  Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger
      7. 6.14.7  Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      8. 6.14.8  Port P7, P7.2, Input/Output With Schmitt Trigger
      9. 6.14.9  Port P7, P7.3, Input/Output With Schmitt Trigger
      10. 6.14.10 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      11. 6.14.11 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      12. 6.14.12 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      13. 6.14.13 Port PU.0, PU.1 Ports
      14. 6.14.14 Port J, PJ.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 6.14.15 Port J, PJ.1 to PJ.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    15. 6.15 Device Descriptors
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 General Layout Recommendations
      6. 7.1.6 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
      1. 8.3.1 Hardware Features
      2. 8.3.2 Recommended Hardware Options
        1. 8.3.2.1 Target Socket Boards
        2. 8.3.2.2 Experimenter Boards
        3. 8.3.2.3 Debugging and Programming Tools
        4. 8.3.2.4 Production Programmers
      3. 8.3.3 Recommended Software Options
        1. 8.3.3.1 Integrated Development Environments
        2. 8.3.3.2 MSP430Ware
        3. 8.3.3.3 TI-RTOS
        4. 8.3.3.4 Command-Line Programmer
    4. 8.4  Documentation Support
    5. 8.5  Receiving Notification of Documentation Updates
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Detailed Description

6.1 Overview

The MSP430F6459 is an ultra-low-power microcontroller that consists of several features which include different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications.

The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in 3 μs (typical).

6.2 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers (see Figure 6-1).

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

For further details, see the CPUX Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU391).

MSP430F6459-HIREL slas566-040.gif Figure 6-1 CPU Registers

6.3 Instruction Set

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 6-1 shows examples of the three types of instruction formats; Table 6-2 shows the address modes.

Table 6-1 Instruction Word Formats

INSTRUCTION WORD FORMAT EXAMPLE OPERATION
Dual operands, source-destination ADD    R4,R5 R4 + R5 → R5
Single operands, destination only CALL    R8 PC → (TOS), R8 → PC
Relative jump, unconditional or conditional JNE Jump-on-equal bit = 0

Table 6-2 Address Mode Descriptions

ADDRESS MODE S(1) D(1) SYNTAX EXAMPLE OPERATION
Register + + MOV Rs,Rd MOV R10,R11 R10 → R11
Indexed + + MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6)
Symbolic (PC relative) + + MOV EDE,TONI M(EDE) → M(TONI)
Absolute + + MOV &MEM, &TCDAT M(MEM) → M(TCDAT)
Indirect + MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)
Indirect auto-increment + MOV @Rn+,Rm MOV @R10+,R11 M(R10) → R11
R10 + 2 → R10
Immediate + MOV #X,TONI MOV #45,TONI #45 → M(TONI)
(1) S = source, D = destination

6.4 Operating Modes

The MCUs have one active mode and seven software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

Software can configure the following operating modes:

  • Active mode (AM)
    • All clocks are active
  • Low-power mode 0 (LPM0)
    • CPU is disabled
    • ACLK and SMCLK remain active, MCLK is disabled
    • FLL loop control remains active
  • Low-power mode 1 (LPM1)
    • CPU is disabled
    • FLL loop control is disabled
    • ACLK and SMCLK remain active, MCLK is disabled
  • Low-power mode 2 (LPM2)
    • CPU is disabled
    • MCLK, FLL loop control, and DCOCLK are disabled
    • DC generator of the DCO remains enabled
    • ACLK remains active
  • Low-power mode 3 (LPM3)
    • CPU is disabled
    • MCLK, FLL loop control, and DCOCLK are disabled
    • DC generator of the DCO is disabled
    • ACLK remains active
  • Low-power mode 4 (LPM4)
    • CPU is disabled
    • ACLK is disabled
    • MCLK, FLL loop control, and DCOCLK are disabled
    • DC generator of the DCO is disabled
    • Crystal oscillator is stopped
    • Complete data retention
  • Low-power mode 3.5 (LPM3.5)
    • Internal regulator disabled
    • No data retention
    • RTC enabled and clocked by low-frequency oscillator
    • Wake-up signal from RST/NMI, RTC_B, P1, P2, P3, and P4
  • Low-power mode 4.5 (LPM4.5)
    • Internal regulator disabled
    • No data retention
    • Wake-up signal from RST/NMI, P1, P2, P3, and P4

6.5 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6-3 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
System Reset
Power-Up, External Reset
Watchdog Time-out, Key Violation
Flash Memory Key Violation
WDTIFG, KEYV (SYSRSTIV)(1) (3) Reset 0FFFEh 63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, SVMLVLRIFG, SVMHVLRIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)(1) (Non)maskable 0FFFCh 62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)(1) (3) (Non)maskable 0FFFAh 61
Comp_B Comparator B interrupt flags (CBIV)(1) (2) Maskable 0FFF8h 60
Timer TB0 TB0CCR0 CCIFG0 (2) Maskable 0FFF6h 59
Timer TB0 TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV)(1) (2)
Maskable 0FFF4h 58
Watchdog Interval Timer Mode WDTIFG Maskable 0FFF2h 57
USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (2) Maskable 0FFF0h 56
USCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (UCB0IV)(1) (2) Maskable 0FFEEh 55
ADC12_A ADC12IFG0 to ADC12IFG15 (ADC12IV)(1) (2) Maskable 0FFECh 54
Timer TA0 TA0CCR0 CCIFG0(2) Maskable 0FFEAh 53
Timer TA0 TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1) (2)
Maskable 0FFE8h 52
LDO-PWR (6) LDOOFFIG, LDOONIFG, LDOOVLIFG Maskable 0FFE6h 51
DMA DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG, DMA4IFG, DMA5IFG (DMAIV)(1) (2) Maskable 0FFE4h 50
Timer TA1 TA1CCR0 CCIFG0(2) Maskable 0FFE2h 49
Timer TA1 TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1) (2)
Maskable 0FFE0h 48
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)(1)(2) Maskable 0FFDEh 47
USCI_A1 Receive or Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (2) Maskable 0FFDCh 46
USCI_B1 Receive or Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (2) Maskable 0FFDAh 45
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)(1) (2) Maskable 0FFD8h 44
LCD_B(5) LCD_B Interrupt Flags (LCDBIV)(1) Maskable 0FFD6h 43
RTC_B RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)(1) (2) Maskable 0FFD4h 42
DAC12_A DAC12_0IFG, DAC12_1IFG(1) (2) Maskable 0FFD2h 41
Timer TA2 TA2CCR0 CCIFG0(2) Maskable 0FFD0h 40
Timer TA2 TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV)(1) (2)
Maskable 0FFCEh 39
I/O Port P3 P3IFG.0 to P3IFG.7 (P3IV)(1) (2) Maskable 0FFCCh 38
I/O Port P4 P4IFG.0 to P4IFG.7 (P4IV)(1) (2) Maskable 0FFCAh 37
USCI_A2 Receive or Transmit UCA2RXIFG, UCA2TXIFG (UCA2IV)(1) (2) 0FFC8h 36
USCI_B2 Receive or Transmit UCB2RXIFG, UCB2TXIFG (UCB2IV)(1) (2) 0FFC6h 35
Reserved Reserved(4) 0FFC4h 34
0FF80h 0, lowest
(1) Multiple source flags
(2) Interrupt flags are in the module.
(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations.
(5) Only on devices with peripheral module LCD_B, otherwise reserved.
(6) Only on devices with peripheral module LDO-PWR.

6.6 Memory Organization

Table 6-4 summarizes the memory map.

Table 6-4 Memory Organization(1)

DESCRIPTION
Memory (flash) Total Size 512KB
Main: interrupt vector 00FFFFh–00FF80h
Main: code memory Bank 3 128KB
087FFFh-068000h
Bank 2 128KB
067FFFh-48000h
Bank 1 128KB
047FFFh-028000h
Bank 0 128KB
027FFFh-008000h
MID support software (ROM) Total Size 1KB
006FFFh-006C00h
RAM Sector 3 16KB
0FBFFFh-0F8000h
Sector 2 16KB
0F7FFFh-0F4000h
Sector 1 16KB
0F3FFFh-0F0000h
Sector 0 16KB
0063FFh–002400h
(mirrored at address range
0FFFFFh-0FC000h)
RAM Sector 7 2KB
0023FFh-001C00h
Information memory (flash) Info A 128 B
0019FFh–001980h
Info B 128 B
00197Fh–001900h
Info C 128 B
0018FFh–001880h
Info D 128 B
00187Fh–001800h
Bootloader (BSL) memory (flash) BSL 3 512 B
0017FFh–001600h
BSL 2 512 B
0015FFh–001400h
BSL 1 512 B
0013FFh–001200h
BSL 0 512 B
0011FFh–001000h
Peripherals Size 4KB
000FFFh–000000h
(1) N/A = Not available

6.7 Bootloader (BSL)

The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the device memory by the BSL is protected by an user-defined password. For complete description of the features of the BSL and its implementation, see MSP430 Programming WIth the Bootloader (BSL) (SLAU319).

6.7.1 UART BSL

MSP4306459 comes preprogrammed with the UART BSL. Use of the UART BSL requires external access to six pins (see Table 6-5).

Table 6-5 UART BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION
RST/NMI/SBWTDIO Entry sequence signal
TEST/SBWTCK Entry sequence signal
P1.1 Data transmit
P1.2 Data receive
VCC Power supply
VSS Ground supply

6.8 JTAG Operation

6.8.1 JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the BSL and its implementation, see the MSP430 Programming With the Bootloader User's Guide (SLAU319).

Table 6-6 JTAG Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION
PJ.3/TCK IN JTAG clock input
PJ.2/TMS IN JTAG state control
PJ.1/TDI/TCLK IN JTAG data input, TCLK input
PJ.0/TDO OUT JTAG data output
TEST/SBWTCK IN Enable JTAG pins
RST/NMI/SBWTDIO IN External reset
VCC Power supply
VSS Ground supply

6.8.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-7 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).

Table 6-7 Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION
TEST/SBWTCK IN Spy-Bi-Wire clock input
RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input and output
VCC Power supply
VSS Ground supply

6.9 Flash Memory

The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include:

  • Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes each. Each segment in main memory is 512 bytes in size.
  • Segments 0 to n may be erased in one step, or each segment may be individually erased.
  • Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory.
  • Segment A can be locked separately.

For further information, see the Flash Controller Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU392).

6.10 Memory Integrity Detection (MID)

The MID is an add-on to the MSP430 flash memory controller. MID provides additional functionality over the regular flash operation methods. Main purpose of the MID function is gaining higher reliability of flash content and overall system integrity in harsh environments and application areas requiring such features. The on-chip MID ROM contains the factory programmed MID support software. This software package provides several software functions that allow to use all MID features.

The MID functionality can be enabled for different flash memory ranges. These memory ranges are selectable by the cw0 parameter of the MID function MidEnable(). Details about address range coverage is listed in Table 6-8.

For further information, see the MID Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU459).

Table 6-8 Address Range Coverage of cw0 Parameter of MidEnable() Function

BITS OF cw0 PARAMETER ADDRESS RANGE
cw0.15 087FFFh-080000h
cw0.14 07FFFFh-078000h
cw0.13 077FFFh-070000h
cw0.12 06FFFFh-068000h
cw0.11 067FFFh-060000h
cw0.10 05FFFFh-058000h
cw0.9 057FFFh-050000h
cw0.8 04FFFFh-048000h
cw0.7 047FFFh-040000h
cw0.6 03FFFFh-038000h
cw0.5 037FFFh-030000h
cw0.4 02FFFFh-028000h
cw0.3 027FFFh-020000h
cw0.2 01FFFFh-018000h
cw0.1 017FFFh-010000h
cw0.0 00FFFFh-008000h

6.11 RAM

The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all data is lost. Features of the RAM include:

  • RAM has n sectors. The size of a sector can be found in Section 6.6.
  • Each sector 0 to n can be complete disabled; however, data retention is lost.
  • Each sector 0 to n automatically enters low-power retention mode when possible.

For further information, see the RAM Controller Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU393).

6.12 Backup RAM

The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during operation from a backup supply if the battery backup system module is implemented.

There are 8 bytes of backup RAM available. It can be word-wise accessed by the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.

For further information, see the Backup RAM Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU394).

6.13 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

6.13.1 Digital I/O

There are up to nine 8-bit I/O ports implemented: P1 through P9 are complete and port PJ contains four individual I/O ports.

  • All individual I/O bits are independently programmable.
  • Any combination of input, output, and interrupt conditions is possible.
  • Programmable pullup or pulldown on all ports.
  • Programmable drive strength on all ports.
  • Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.
  • Read and write access to port-control registers is supported by all instructions.
  • Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).

For further information, see the Digital I/O Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU396).

6.13.2 Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2. Table 6-9 lists the available mappings, and Table 6-10 lists the default settings.

For further information, see the Port Mapping Controller Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU397).

Table 6-9 Port Mapping Mnemonics and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
1 PM_CBOUT Comparator_B output
PM_TB0CLK Timer TB0 clock input
2 PM_ADC12CLK ADC12CLK
PM_DMAE0 DMAE0 Input
3 PM_SVMOUT SVM output
PM_TB0OUTH Timer TB0 high impedance input TB0OUTH
4 PM_TB0CCR0B Timer TB0 CCR0 capture input CCI0B Timer TB0: TB0.0 compare output Out0
5 PM_TB0CCR1B Timer TB0 CCR1 capture input CCI1B Timer TB0: TB0.1 compare output Out1
6 PM_TB0CCR2B Timer TB0 CCR2 capture input CCI2B Timer TB0: TB0.2 compare output Out2
7 PM_TB0CCR3B Timer TB0 CCR3 capture input CCI3B Timer TB0: TB0.3 compare output Out3
8 PM_TB0CCR4B Timer TB0 CCR4 capture input CCI4B Timer TB0: TB0.4 compare output Out4
9 PM_TB0CCR5B Timer TB0 CCR5 capture input CCI5B Timer TB0: TB0.5 compare output Out5
10 PM_TB0CCR6B Timer TB0 CCR6 capture input CCI6B Timer TB0: TB0.6 compare output Out6
11 PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI - input)
PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)
12 PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI - output)
PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
13 PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
14 PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
15 PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
16 PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
17 PM_MCLK MCLK
18 Reserved Reserved for test purposes. Do not use this setting.
19 Reserved Reserved for test purposes. Do not use this setting.
20-30 Reserved None DVSS
31 (0FFh)(1) PM_ANALOG Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are ignored, which results in a read out value of 31.

Table 6-10 Default Mapping

PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
P2.0/P2MAP0 PM_UCB0STE,
PM_UCA0CLK

USCI_B0 SPI slave transmit enable (direction controlled by USCI - input),

USCI_A0 clock input/output (direction controlled by USCI)

P2.1/P2MAP1 PM_UCB0SIMO,
PM_UCB0SDA

USCI_B0 SPI slave in master out (direction controlled by USCI),

USCI_B0 I2C data (open drain and direction controlled by USCI)

P2.2/P2MAP2 PM_UCB0SOMI,
PM_UCB0SCL

USCI_B0 SPI slave out master in (direction controlled by USCI),

USCI_B0 I2C clock (open drain and direction controlled by USCI)

P2.3/P2MAP3 PM_UCB0CLK,
PM_UCA0STE

USCI_B0 clock input/output (direction controlled by USCI),

USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)

P2.4/P2MAP4 PM_UCA0TXD,
PM_UCA0SIMO

USCI_A0 UART TXD (direction controlled by USCI - output),

USCI_A0 SPI slave in master out (direction controlled by USCI)

P2.5/P2MAP5 PM_UCA0RXD,
PM_UCA0SOMI

USCI_A0 UART RXD (direction controlled by USCI - input),

USCI_A0 SPI slave out master in (direction controlled by USCI)

P2.6/P2MAP6/ R03 PM_NONE DVSS
P2.7/P2MAP7/LCDREF/R13 PM_NONE DVSS

6.13.3 Oscillator and System Clock

The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32-kHz watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator (XT2). The UCS module is designed to meet the requirements of both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turnon clock source and stabilizes in 3 µs (typical). The UCS module provides the following clock signals:

  • Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally-controlled oscillator DCO.
  • Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources available to ACLK.
  • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources available to ACLK.
  • ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

For further information, see the UCS Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU390).

6.13.4 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

For further information, see the PMM Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU388).

6.13.5 Hardware Multiplier (MPY)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations.

For further information, see the MPY Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU404).

6.13.6 Real-Time Clock (RTC_B)

The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds, minutes, hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in LPM3.5 mode and operation from a backup supply.

The application report Using the MSP430 RTC_B Module With Battery Backup Supply (SLAA665) describes how to use the RTC_B with battery backup supply functionality to retain the time and keep the RTC counting through loss of main power supply, as well as how to handle correct reinitialization when the main power supply is restored.

For further information, see the RTC_B Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU403).

6.13.7 Watchdog Timer (WDT_A)

The primary function of the WDT_A module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

For further information, see the WDT_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU399).

6.13.8 System Module (SYS)

The SYS module handles many of the system functions within the device. These include power-on reset and power-up clear handling, NMI source selection and management, reset interrupt vector generators (see Table 6-11), bootloader entry mechanisms, and configuration management (device descriptors). SYS also includes a data exchange mechanism using JTAG called a JTAG mailbox that can be used in the application.

For further information, see the SYS Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU387).

Table 6-11 System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER INTERRUPT EVENT WORD ADDRESS OFFSET PRIORITY
SYSRSTIV, System Reset No interrupt pending 019Eh 00h
Brownout (BOR) 02h Highest
RST/NMI (BOR) 04h
PMMSWBOR (BOR) 06h
LPM3.5 or LPM4.5 wakeup (BOR) 08h
Security violation (BOR) 0Ah
SVSL (POR) 0Ch
SVSH (POR) 0Eh
SVML_OVP (POR) 10h
SVMH_OVP (POR) 12h
PMMSWPOR (POR) 14h
WDT time-out (PUC) 16h
WDT key violation (PUC) 18h
KEYV flash key violation (PUC) 1Ah
Reserved 1Ch
Peripheral area fetch (PUC) 1Eh
PMM key violation (PUC) 20h
Reserved 22h to 3Eh Lowest
SYSSNIV, System NMI No interrupt pending 019Ch 00h
SVMLIFG 02h Highest
SVMHIFG 04h
DLYLIFG 06h
DLYHIFG 08h
VMAIFG 0Ah
JMBINIFG 0Ch
JMBOUTIFG 0Eh
SVMLVLRIFG 10h
SVMHVLRIFG 12h
Reserved 14h to 1Eh Lowest
SYSUNIV, User NMI No interrupt pending 019Ah 00h
NMIIFG 02h Highest
OFIFG 04h
ACCVIFG 06h
BUSIFG 08h
Reserved 0Ah to 1Eh Lowest
SYSBERRIV, Bus Error No interrupt pending 0198h 00h
Reserved 02h Highest
04h
MID error 06h
Reserved 08h to 1Eh Lowest

6.13.9 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral.

For further information, see the DMA Controller Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU395).

Table 6-12 DMA Trigger Assignments(1)

TRIGGER CHANNEL
0 1 2 3 4 5
0 DMAREQ
1 TA0CCR0 CCIFG
2 TA0CCR2 CCIFG
3 TA1CCR0 CCIFG
4 TA1CCR2 CCIFG
5 TA2CCR0 CCIFG
6 TA2CCR2 CCIFG
7 TBCCR0 CCIFG
8 TBCCR2 CCIFG
9 Reserved
10 Reserved
11 Reserved
12 UCA2RXIFG
13 UCA2TXIFG
14 UCB2RXIFG
15 UCB2TXIFG
16 UCA0RXIFG
17 UCA0TXIFG
18 UCB0RXIFG
19 UCB0TXIFG
20 UCA1RXIFG
21 UCA1TXIFG
22 UCB1RXIFG
23 UCB1TXIFG
24 ADC12IFGx
25 DAC12_0IFG
26 DAC12_1IFG
27 Reserved
28 Reserved
29 MPY ready
30 DMA5IFG DMA0IFG DMA1IFG DMA2IFG DMA3IFG DMA4IFG
31 DMAE0
(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not cause any DMA trigger event when selected.

6.13.10 Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions, A and B.

The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA.

The USCI_Bn module provides support for SPI (3-pin or 4-pin) or I2C.

The MSP430F665x, MSP430F645x, MSP430F565x, MSP430F535x series includes three complete USCI modules (n = 0 to 2).

For further information, see the following User's Guides:

  • USCI UART Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU410)
  • USCI SPI Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU411)
  • USCI I2C Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU412)

6.13.11 Timer TA0

Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers (see Table 6-13). TA0 supports multiple capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

For further information, see the Timer_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU400).

Table 6-13 Timer TA0 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT SIGNAL MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL OUTPUT PIN NUMBER
34-P1.0 TA0CLK TACLK Timer NA NA
ACLK ACLK
SMCLK SMCLK
34-P1.0 TA0CLK TACLK
35-P1.1 TA0.0 CCI0A CCR0 TA0 TA0.0 35-P1.1
DVSS CCI0B
DVSS GND
DVCC VCC
36-P1.2 TA0.1 CCI1A CCR1 TA1 TA0.1 36-P1.2
40-P1.6 TA0.1 CCI1B 40-P1.6
DVSS GND ADC12_A (internal)
ADC12SHSx = {1}
DVCC VCC
37-P1.3 TA0.2 CCI2A CCR2 TA2 TA0.2 37-P1.3
41-P1.7 TA0.2 CCI2B 41-P1.7
DVSS GND
DVCC VCC
38-P1.4 TA0.3 CCI3A CCR3 TA3 TA0.3 38-P1.4
DVSS CCI3B
DVSS GND
DVCC VCC
39-P1.5 TA0.4 CCI4A CCR4 TA4 TA0.4 39-P1.5
DVSS CCI4B
DVSS GND
DVCC VCC

6.13.12 Timer TA1

Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers (see Table 6-14). TA1 supports multiple capture/compares, PWM outputs, and interval timing. TA1 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

For further information, see the Timer_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU400).

Table 6-14 Timer TA1 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT SIGNAL MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL OUTPUT PIN NUMBER
42-P3.0 TA1CLK TACLK Timer NA NA
ACLK ACLK
SMCLK SMCLK
42-P3.0 TA1CLK TACLK
43-P3.1 TA1.0 CCI0A CCR0 TA0 TA1.0 43-P3.1
DVSS CCI0B
DVSS GND
DVCC VCC
44-P3.2 TA1.1 CCI1A CCR1 TA1 TA1.1 44-P3.2
CBOUT (internal) CCI1B DAC12_A
DAC12_0, DAC12_1 (internal)
DVSS GND
DVCC VCC
45-P3.3 TA1.2 CCI2A CCR2 TA2 TA1.2 45-P3.3
ACLK (internal) CCI2B
DVSS GND
DVCC VCC

6.13.13 Timer TA2

Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers (see Table 6-15). TA2 supports multiple capture/compares, PWM outputs, and interval timing. TA2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

For further information, see the Timer_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU400).

Table 6-15 Timer TA2 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT SIGNAL MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL OUTPUT PIN NUMBER
46-P3.4 TA2CLK TACLK Timer NA NA
ACLK ACLK
SMCLK SMCLK
46-P3.4 TA2CLK TACLK
47-P3.5 TA2.0 CCI0A CCR0 TA0 TA2.0 47-P3.5
DVSS CCI0B
DVSS GND
DVCC VCC
48-P3.6 TA2.1 CCI1A CCR1 TA1 TA2.1 48-P3.6
CBOUT (internal) CCI1B
DVSS GND
DVCC VCC
49-P3.7 TA2.2 CCI2A CCR2 TA2 TA2.2 49-P3.7
ACLK (internal) CCI2B
DVSS GND
DVCC VCC

6.13.14 Timer TB0

Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers (see Table 6-16). TB0 supports multiple capture/compares, PWM outputs, and interval timing. TB0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

For further information, see the Timer_B Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU401).

Table 6-16 Timer TB0 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT SIGNAL MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL OUTPUT PIN NUMBER
58-P8.0
P2MAPx(1)
TB0CLK TB0CLK Timer NA NA
ACLK ACLK
SMCLK SMCLK
58-P8.0
P2MAPx(1)
TB0CLK TB0CLK
50-P4.0 TB0.0 CCI0A CCR0 TB0 TB0.0 50-P4.0
P2MAPx(1) TB0.0 CCI0B P2MAPx(1)
DVSS GND ADC12 (internal)
ADC12SHSx = {2}
DVCC VCC
51-P4.1 TB0.1 CCI1A CCR1 TB1 TB0.1 51-P4.1
P2MAPx(1) TB0.1 CCI1B P2MAPx(1)
DVSS GND ADC12 (internal)
ADC12SHSx = {3}
DVCC VCC
52-P4.2 TB0.2 CCI2A CCR2 TB2 TB0.2 52-P4.2
P2MAPx(1) TB0.2 CCI2B P2MAPx(1)
DVSS GND DAC12_A
DAC12_0, DAC12_1 (internal)
DVCC VCC
53-P4.3 TB0.3 CCI3A CCR3 TB3 TB0.3 53-P4.3
P2MAPx(1) TB0.3 CCI3B P2MAPx(1)
DVSS GND
DVCC VCC
54-P4.4 TB0.4 CCI4A CCR4 TB4 TB0.4 54-P4.4
P2MAPx(1) TB0.4 CCI4B P2MAPx(1)
DVSS GND
DVCC VCC
55-P4.5 TB0.5 CCI5A CCR5 TB5 TB0.5 55-P4.5
P2MAPx(1) TB0.5 CCI5B P2MAPx(1)
DVSS GND
DVCC VCC
56-P4.6 TB0.6 CCI6A CCR6 TB6 TB0.6 56-P4.6
P2MAPx(1) TB0.6 CCI6B P2MAPx(1)
DVSS GND
DVCC VCC
(1) Timer functions are selectable through the port mapping controller.

6.13.15 Comparator_B

The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals.

For further information, see the COMP_B Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU408).

6.13.16 ADC12_A

The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.

For further information, see the ADC12_A Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU406).

6.13.17 DAC12_A

The DAC12_A module is a 12-bit, R-ladder, voltage output DAC. The DAC12_A may be used in 8-bit or 12-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12_A modules are present, they may be grouped together for synchronous operation.

6.13.18 CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

For further information, see the CRC Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU398).

6.13.19 Voltage Reference (REF) Module

The REF module is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device.

For further information, see the REF Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU405).

6.13.20 LCD_B

The LCD_B driver generates the segment and common signals that are required to drive a liquid crystal display (LCD). The LCD_B controller has dedicated data memories to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is possible to control the level of the LCD voltage, and thus contrast, by software. The module also provides an automatic blinking capability for individual segments.

The LCD_B module is only available on the MSP430F665x and MSP430F645x devices.

For further information, see the LCD_B Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU409).

6.13.21 LDO and PU Port

The integrated 3.3-V power system incorporates an integrated 3.3-V LDO regulator that allows the entire MSP430 microcontroller to be powered from nominal 5-V LDOI when it is made available for the system. Alternatively, the power system can supply power only to other components within the system, or it can be unused altogether.

The Port U Pins (PU.0 and PU.1) function as general-purpose high-current I/O pins. These pins can only be configured together as either both inputs or both outputs. Port U is supplied by the LDOO rail. If the 3.3-V LDO is not being used in the system (disabled), the LDOO pin can be supplied externally.

The LDO-PWR module (LDO and PU Port) is only available on the MSP430F645x and MSP430F535x devices.

6.13.22 Embedded Emulation Module (EEM) (L Version)

The EEM supports real-time in-system debugging. The L version of the EEM has the following features:

  • Eight hardware triggers or breakpoints on memory access
  • Two hardware triggers or breakpoints on CPU register write access
  • Up to ten hardware triggers can be combined to form complex triggers or breakpoints
  • Two cycle counters
  • Sequencer
  • State storage
  • Clock control on module level

For further information, see the EEM Module (Chapter Excerpt From MSP430x5xx Family, SLAU208) (SLAU414).

6.13.23 Peripheral File Map

Table 6-17 lists the base register address for each available peripheral.

Table 6-17 Peripherals

MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE(1)
Special Functions (see Table 6-18) 0100h 000h-01Fh
PMM (see Table 6-19) 0120h 000h-010h
Flash Control (see Table 6-20) 0140h 000h-00Fh
CRC16 (see Table 6-21) 0150h 000h-007h
RAM Control (see Table 6-22) 0158h 000h-001h
Watchdog (see Table 6-23) 015Ch 000h-001h
UCS (see Table 6-24) 0160h 000h-01Fh
SYS (see Table 6-25) 0180h 000h-01Fh
Shared Reference (see Table 6-26) 01B0h 000h-001h
Port Mapping Control (see Table 6-27) 01C0h 000h-003h
Port Mapping Port P2 (see Table 6-27) 01D0h 000h-007h
Port P1, P2 (see Table 6-28) 0200h 000h-01Fh
Port P3, P4 (see Table 6-29) 0220h 000h-01Fh
Port P5, P6 (see Table 6-30) 0240h 000h-00Bh
Port P7, P8 (see Table 6-31) 0260h 000h-00Bh
Port P9 (see Table 6-32) 0280h 000h-00Bh
Port PJ (see Table 6-33) 0320h 000h-01Fh
Timer TA0 (see Table 6-34) 0340h 000h-02Eh
Timer TA1 (see Table 6-35) 0380h 000h-02Eh
Timer TB0 (see Table 6-36) 03C0h 000h-02Eh
Timer TA2 (see Table 6-37) 0400h 000h-02Eh
Battery Backup (see Table 6-38) 0480h 000h-01Fh
RTC_B (see Table 6-39) 04A0h 000h-01Fh
32-Bit Hardware Multiplier (see Table 6-40) 04C0h 000h-02Fh
DMA General Control (see Table 6-41) 0500h 000h-00Fh
DMA Channel 0 (see Table 6-41) 0510h 000h-00Ah
DMA Channel 1 (see Table 6-41) 0520h 000h-00Ah
DMA Channel 2 (see Table 6-41) 0530h 000h-00Ah
DMA Channel 3 (see Table 6-41) 0540h 000h-00Ah
DMA Channel 4 (see Table 6-41) 0550h 000h-00Ah
DMA Channel 5 (see Table 6-41) 0560h 000h-00Ah
USCI_A0 (see Table 6-42) 05C0h 000h-01Fh
USCI_B0 (see Table 6-43) 05E0h 000h-01Fh
USCI_A1 (see Table 6-44) 0600h 000h-01Fh
USCI_B1 (see Table 6-45) 0620h 000h-01Fh
USCI_A2 (see Table 6-46) 0640h 000h-01Fh
USCI_B2 (see Table 6-47) 0660h 000h-01Fh
ADC12_A (see Table 6-48) 0700h 000h-03Fh
DAC12_A (see Table 6-49) 0780h 000h-01Fh
Comparator_B (see Table 6-50) 08C0h 000h-00Fh
LDO-PWR; LDO and Port U configuration (see Table 6-51) (2) 0900h 000h-014h
LCD_B control (see Table 6-52) (3) 0A00h 000h-05Fh
(1) For a detailed description of the individual control register offset addresses, see the MSP430F5xx and MSP430F6xx Family User's Guide (SLAU208).
(2) Only on devices with peripheral module LDO-PWR.
(3) Only on devices with peripheral module LCD_B.

Table 6-18 Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION REGISTER OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h

Table 6-19 PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION REGISTER OFFSET
PMM control 0 PMMCTL0 00h
PMM control 1 PMMCTL1 02h
SVS high-side control SVSMHCTL 04h
SVS low-side control SVSMLCTL 06h
PMM interrupt flags PMMIFG 0Ch
PMM interrupt enable PMMIE 0Eh
PMM power mode 5 control PM5CTL0 10h

Table 6-20 Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION REGISTER OFFSET
Flash control 1 FCTL1 00h
Flash control 3 FCTL3 04h
Flash control 4 FCTL4 06h

Table 6-21 CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION REGISTER OFFSET
CRC data input CRC16DI 00h
CRC result CRC16INIRES 04h

Table 6-22 RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION REGISTER OFFSET
RAM control 0 RCCTL0 00h

Table 6-23 Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION REGISTER OFFSET
Watchdog timer control WDTCTL 00h

Table 6-24 UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION REGISTER OFFSET
UCS control 0 UCSCTL0 00h
UCS control 1 UCSCTL1 02h
UCS control 2 UCSCTL2 04h
UCS control 3 UCSCTL3 06h
UCS control 4 UCSCTL4 08h
UCS control 5 UCSCTL5 0Ah
UCS control 6 UCSCTL6 0Ch
UCS control 7 UCSCTL7 0Eh
UCS control 8 UCSCTL8 10h

Table 6-25 SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION REGISTER OFFSET
System control SYSCTL 00h
Bootloader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
Bus error vector generator SYSBERRIV 18h
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh

Table 6-26 Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION REGISTER OFFSET
Shared reference control REFCTL 00h

Table 6-27 Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P4: 01D0h)

REGISTER DESCRIPTION REGISTER OFFSET
Port mapping password PMAPPWD 00h
Port mapping control PMAPCTL 02h
Port P2.0 mapping P2MAP0 00h
Port P2.1 mapping P2MAP1 01h
Port P2.2 mapping P2MAP2 02h
Port P2.3 mapping P2MAP3 03h
Port P2.4 mapping P2MAP4 04h
Port P2.5 mapping P2MAP5 05h
Port P2.6 mapping P2MAP6 06h
Port P2.7 mapping P2MAP7 07h

Table 6-28 Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 pullup/pulldown enable P1REN 06h
Port P1 drive strength P1DS 08h
Port P1 selection P1SEL 0Ah
Port P1 interrupt vector word P1IV 0Eh
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 input P2IN 01h
Port P2 output P2OUT 03h
Port P2 direction P2DIR 05h
Port P2 pullup/pulldown enable P2REN 07h
Port P2 drive strength P2DS 09h
Port P2 selection P2SEL 0Bh
Port P2 interrupt vector word P2IV 1Eh
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt flag P2IFG 1Dh

Table 6-29 Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P3 input P3IN 00h
Port P3 output P3OUT 02h
Port P3 direction P3DIR 04h
Port P3 pullup/pulldown enable P3REN 06h
Port P3 drive strength P3DS 08h
Port P3 selection P3SEL 0Ah
Port P3 interrupt vector word P3IV 0Eh
Port P3 interrupt edge select P3IES 18h
Port P3 interrupt enable P3IE 1Ah
Port P3 interrupt flag P3IFG 1Ch
Port P4 input P4IN 01h
Port P4 output P4OUT 03h
Port P4 direction P4DIR 05h
Port P4 pullup/pulldown enable P4REN 07h
Port P4 drive strength P4DS 09h
Port P4 selection P4SEL 0Bh
Port P4 interrupt vector word P4IV 1Eh
Port P4 interrupt edge select P4IES 19h
Port P4 interrupt enable P4IE 1Bh
Port P4 interrupt flag P4IFG 1Dh

Table 6-30 Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P5 input P5IN 00h
Port P5 output P5OUT 02h
Port P5 direction P5DIR 04h
Port P5 pullup/pulldown enable P5REN 06h
Port P5 drive strength P5DS 08h
Port P5 selection P5SEL 0Ah
Port P6 input P6IN 01h
Port P6 output P6OUT 03h
Port P6 direction P6DIR 05h
Port P6 pullup/pulldown enable P6REN 07h
Port P6 drive strength P6DS 09h
Port P6 selection P6SEL 0Bh

Table 6-31 Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P7 input P7IN 00h
Port P7 output P7OUT 02h
Port P7 direction P7DIR 04h
Port P7 pullup/pulldown enable P7REN 06h
Port P7 drive strength P7DS 08h
Port P7 selection P7SEL 0Ah
Port P8 input P8IN 01h
Port P8 output P8OUT 03h
Port P8 direction P8DIR 05h
Port P8 pullup/pulldown enable P8REN 07h
Port P8 drive strength P8DS 09h
Port P8 selection P8SEL 0Bh

Table 6-32 Port P9 Register (Base Address: 0280h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P9 input P9IN 00h
Port P9 output P9OUT 02h
Port P9 direction P9DIR 04h
Port P9 pullup/pulldown enable P9REN 06h
Port P9 drive strength P9DS 08h
Port P9 selection P9SEL 0Ah

Table 6-33 Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION REGISTER OFFSET
Port PJ input PJIN 00h
Port PJ output PJOUT 02h
Port PJ direction PJDIR 04h
Port PJ pullup/pulldown enable PJREN 06h
Port PJ drive strength PJDS 08h

Table 6-34 TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION REGISTER OFFSET
TA0 control TA0CTL 00h
Capture/compare control 0 TA0CCTL0 02h
Capture/compare control 1 TA0CCTL1 04h
Capture/compare control 2 TA0CCTL2 06h
Capture/compare control 3 TA0CCTL3 08h
Capture/compare control 4 TA0CCTL4 0Ah
TA0 counter TA0R 10h
Capture/compare 0 TA0CCR0 12h
Capture/compare 1 TA0CCR1 14h
Capture/compare 2 TA0CCR2 16h
Capture/compare 3 TA0CCR3 18h
Capture/compare 4 TA0CCR4 1Ah
TA0 expansion 0 TA0EX0 20h
TA0 interrupt vector TA0IV 2Eh

Table 6-35 TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION REGISTER OFFSET
TA1 control TA1CTL 00h
Capture/compare control 0 TA1CCTL0 02h
Capture/compare control 1 TA1CCTL1 04h
Capture/compare control 2 TA1CCTL2 06h
TA1 counter TA1R 10h
Capture/compare 0 TA1CCR0 12h
Capture/compare 1 TA1CCR1 14h
Capture/compare 2 TA1CCR2 16h
TA1 expansion 0 TA1EX0 20h
TA1 interrupt vector TA1IV 2Eh

Table 6-36 TB0 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION REGISTER OFFSET
TB0 control TB0CTL 00h
Capture/compare control 0 TB0CCTL0 02h
Capture/compare control 1 TB0CCTL1 04h
Capture/compare control 2 TB0CCTL2 06h
Capture/compare control 3 TB0CCTL3 08h
Capture/compare control 4 TB0CCTL4 0Ah
Capture/compare control 5 TB0CCTL5 0Ch
Capture/compare control 6 TB0CCTL6 0Eh
TB0 counter TB0R 10h
Capture/compare 0 TB0CCR0 12h
Capture/compare 1 TB0CCR1 14h
Capture/compare 2 TB0CCR2 16h
Capture/compare 3 TB0CCR3 18h
Capture/compare 4 TB0CCR4 1Ah
Capture/compare 5 TB0CCR5 1Ch
Capture/compare 6 TB0CCR6 1Eh
TB0 expansion 0 TB0EX0 20h
TB0 interrupt vector TB0IV 2Eh

Table 6-37 TA2 Registers (Base Address: 0400h)

REGISTER DESCRIPTION REGISTER OFFSET
TA2 control TA2CTL 00h
Capture/compare control 0 TA2CCTL0 02h
Capture/compare control 1 TA2CCTL1 04h
Capture/compare control 2 TA2CCTL2 06h
TA2 counter TA2R 10h
Capture/compare 0 TA2CCR0 12h
Capture/compare 1 TA2CCR1 14h
Capture/compare 2 TA2CCR2 16h
TA2 expansion 0 TA2EX0 20h
TA2 interrupt vector TA2IV 2Eh

Table 6-38 Battery Backup Registers (Base Address: 0480h)

REGISTER DESCRIPTION REGISTER OFFSET
Battery backup memory 0 BAKMEM0 00h
Battery backup memory 1 BAKMEM1 02h
Battery backup memory 2 BAKMEM2 04h
Battery backup memory 3 BAKMEM3 06h
Battery backup control BAKCTL 1Ch
Battery charger control BAKCHCTL 1Eh

Table 6-39 Real-Time Clock Registers (Base Address: 04A0h)

REGISTER DESCRIPTION REGISTER OFFSET
RTC control 0 RTCCTL0 00h
RTC control 1 RTCCTL1 01h
RTC control 2 RTCCTL2 02h
RTC control 3 RTCCTL3 03h
RTC prescaler 0 control RTCPS0CTL 08h
RTC prescaler 1 control RTCPS1CTL 0Ah
RTC prescaler 0 RTCPS0 0Ch
RTC prescaler 1 RTCPS1 0Dh
RTC interrupt vector word RTCIV 0Eh
RTC seconds RTCSEC 10h
RTC minutes RTCMIN 11h
RTC hours RTCHOUR 12h
RTC day of week RTCDOW 13h
RTC days RTCDAY 14h
RTC month RTCMON 15h
RTC year low RTCYEARL 16h
RTC year high RTCYEARH 17h
RTC alarm minutes RTCAMIN 18h
RTC alarm hours RTCAHOUR 19h
RTC alarm day of week RTCADOW 1Ah
RTC alarm days RTCADAY 1Bh
Binary-to-BCD conversion BIN2BCD 1Ch
BCD-to-binary conversion BCD2BIN 1Eh

Table 6-40 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION REGISTER OFFSET
16-bit operand 1 – multiply MPY 00h
16-bit operand 1 – signed multiply MPYS 02h
16-bit operand 1 – multiply accumulate MAC 04h
16-bit operand 1 – signed multiply accumulate MACS 06h
16-bit operand 2 OP2 08h
16 × 16 result low word RESLO 0Ah
16 × 16 result high word RESHI 0Ch
16 × 16 sum extension SUMEXT 0Eh
32-bit operand 1 – multiply low word MPY32L 10h
32-bit operand 1 – multiply high word MPY32H 12h
32-bit operand 1 – signed multiply low word MPYS32L 14h
32-bit operand 1 – signed multiply high word MPYS32H 16h
32-bit operand 1 – multiply accumulate low word MAC32L 18h
32-bit operand 1 – multiply accumulate high word MAC32H 1Ah
32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 – low word OP2L 20h
32-bit operand 2 – high word OP2H 22h
32 × 32 result 0 – least significant word RES0 24h
32 × 32 result 1 RES1 26h
32 × 32 result 2 RES2 28h
32 × 32 result 3 – most significant word RES3 2Ah
MPY32 control 0 MPY32CTL0 2Ch

Table 6-41 DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA Channel 4: 0550h, DMA Channel 5: 0560h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA general control: DMA module control 0 DMACTL0 00h
DMA general control: DMA module control 1 DMACTL1 02h
DMA general control: DMA module control 2 DMACTL2 04h
DMA general control: DMA module control 3 DMACTL3 06h
DMA general control: DMA module control 4 DMACTL4 08h
DMA general control: DMA interrupt vector DMAIV 0Ah
DMA channel 0 control DMA0CTL 00h
DMA channel 0 source address low DMA0SAL 02h
DMA channel 0 source address high DMA0SAH 04h
DMA channel 0 destination address low DMA0DAL 06h
DMA channel 0 destination address high DMA0DAH 08h
DMA channel 0 transfer size DMA0SZ 0Ah
DMA channel 1 control DMA1CTL 00h
DMA channel 1 source address low DMA1SAL 02h
DMA channel 1 source address high DMA1SAH 04h
DMA channel 1 destination address low DMA1DAL 06h
DMA channel 1 destination address high DMA1DAH 08h
DMA channel 1 transfer size DMA1SZ 0Ah
DMA channel 2 control DMA2CTL 00h
DMA channel 2 source address low DMA2SAL 02h
DMA channel 2 source address high DMA2SAH 04h
DMA channel 2 destination address low DMA2DAL 06h
DMA channel 2 destination address high DMA2DAH 08h
DMA channel 2 transfer size DMA2SZ 0Ah
DMA channel 3 control DMA3CTL 00h
DMA channel 3 source address low DMA3SAL 02h
DMA channel 3 source address high DMA3SAH 04h
DMA channel 3 destination address low DMA3DAL 06h
DMA channel 3 destination address high DMA3DAH 08h
DMA channel 3 transfer size DMA3SZ 0Ah
DMA channel 4 control DMA4CTL 00h
DMA channel 4 source address low DMA4SAL 02h
DMA channel 4 source address high DMA4SAH 04h
DMA channel 4 destination address low DMA4DAL 06h
DMA channel 4 destination address high DMA4DAH 08h
DMA channel 4 transfer size DMA4SZ 0Ah
DMA channel 5 control DMA5CTL 00h
DMA channel 5 source address low DMA5SAL 02h
DMA channel 5 source address high DMA5SAH 04h
DMA channel 5 destination address low DMA5DAL 06h
DMA channel 5 destination address high DMA5DAH 08h
DMA channel 5 transfer size DMA5SZ 0Ah

Table 6-42 USCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI control 0 UCA0CTL0 00h
USCI control 1 UCA0CTL1 01h
USCI baud rate 0 UCA0BR0 06h
USCI baud rate 1 UCA0BR1 07h
USCI modulation control UCA0MCTL 08h
USCI status UCA0STAT 0Ah
USCI receive buffer UCA0RXBUF 0Ch
USCI transmit buffer UCA0TXBUF 0Eh
USCI LIN control UCA0ABCTL 10h
USCI IrDA transmit control UCA0IRTCTL 12h
USCI IrDA receive control UCA0IRRCTL 13h
USCI interrupt enable UCA0IE 1Ch
USCI interrupt flags UCA0IFG 1Dh
USCI interrupt vector word UCA0IV 1Eh

Table 6-43 USCI_B0 Registers (Base Address: 05E0h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 0 UCB0CTL0 00h
USCI synchronous control 1 UCB0CTL1 01h
USCI synchronous bit rate 0 UCB0BR0 06h
USCI synchronous bit rate 1 UCB0BR1 07h
USCI synchronous status UCB0STAT 0Ah
USCI synchronous receive buffer UCB0RXBUF 0Ch
USCI synchronous transmit buffer UCB0TXBUF 0Eh
USCI I2C own address UCB0I2COA 10h
USCI I2C slave address UCB0I2CSA 12h
USCI interrupt enable UCB0IE 1Ch
USCI interrupt flags UCB0IFG 1Dh
USCI interrupt vector word UCB0IV 1Eh

Table 6-44 USCI_A1 Registers (Base Address: 0600h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI control 0 UCA1CTL0 00h
USCI control 1 UCA1CTL1 01h
USCI baud rate 0 UCA1BR0 06h
USCI baud rate 1 UCA1BR1 07h
USCI modulation control UCA1MCTL 08h
USCI status UCA1STAT 0Ah
USCI receive buffer UCA1RXBUF 0Ch
USCI transmit buffer UCA1TXBUF 0Eh
USCI LIN control UCA1ABCTL 10h
USCI IrDA transmit control UCA1IRTCTL 12h
USCI IrDA receive control UCA1IRRCTL 13h
USCI interrupt enable UCA1IE 1Ch
USCI interrupt flags UCA1IFG 1Dh
USCI interrupt vector word UCA1IV 1Eh

Table 6-45 USCI_B1 Registers (Base Address: 0620h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 0 UCB1CTL0 00h
USCI synchronous control 1 UCB1CTL1 01h
USCI synchronous bit rate 0 UCB1BR0 06h
USCI synchronous bit rate 1 UCB1BR1 07h
USCI synchronous status UCB1STAT 0Ah
USCI synchronous receive buffer UCB1RXBUF 0Ch
USCI synchronous transmit buffer UCB1TXBUF 0Eh
USCI I2C own address UCB1I2COA 10h
USCI I2C slave address UCB1I2CSA 12h
USCI interrupt enable UCB1IE 1Ch
USCI interrupt flags UCB1IFG 1Dh
USCI interrupt vector word UCB1IV 1Eh

Table 6-46 USCI_A2 Registers (Base Address: 0640h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI control 0 UCA2CTL0 00h
USCI control 1 UCA2CTL1 01h
USCI baud rate 0 UCA2BR0 06h
USCI baud rate 1 UCA2BR1 07h
USCI modulation control UCA2MCTL 08h
USCI status UCA2STAT 0Ah
USCI receive buffer UCA2RXBUF 0Ch
USCI transmit buffer UCA2TXBUF 0Eh
USCI LIN control UCA2ABCTL 10h
USCI IrDA transmit control UCA2IRTCTL 12h
USCI IrDA receive control UCA2IRRCTL 13h
USCI interrupt enable UCA2IE 1Ch
USCI interrupt flags UCA2IFG 1Dh
USCI interrupt vector word UCA2IV 1Eh

Table 6-47 USCI_B2 Registers (Base Address: 0660h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 0 UCB2CTL0 00h
USCI synchronous control 1 UCB2CTL1 01h
USCI synchronous bit rate 0 UCB2BR0 06h
USCI synchronous bit rate 1 UCB2BR1 07h
USCI synchronous status UCB2STAT 0Ah
USCI synchronous receive buffer UCB2RXBUF 0Ch
USCI synchronous transmit buffer UCB2TXBUF 0Eh
USCI I2C own address UCB2I2COA 10h
USCI I2C slave address UCB2I2CSA 12h
USCI interrupt enable UCB2IE 1Ch
USCI interrupt flags UCB2IFG 1Dh
USCI interrupt vector word UCB2IV 1Eh

Table 6-48 ADC12_A Registers (Base Address: 0700h)

REGISTER DESCRIPTION REGISTER OFFSET
ADC12 control 0 ADC12CTL0 00h
ADC12 control 1 ADC12CTL1 02h
ADC12 control 2 ADC12CTL2 04h
Interrupt flag ADC12IFG 0Ah
Interrupt enable ADC12IE 0Ch
Interrupt vector word ADC12IV 0Eh
ADC memory control 0 ADC12MCTL0 10h
ADC memory control 1 ADC12MCTL1 11h
ADC memory control 2 ADC12MCTL2 12h
ADC memory control 3 ADC12MCTL3 13h
ADC memory control 4 ADC12MCTL4 14h
ADC memory control 5 ADC12MCTL5 15h
ADC memory control 6 ADC12MCTL6 16h
ADC memory control 7 ADC12MCTL7 17h
ADC memory control 8 ADC12MCTL8 18h
ADC memory control 9 ADC12MCTL9 19h
ADC memory control 10 ADC12MCTL10 1Ah
ADC memory control 11 ADC12MCTL11 1Bh
ADC memory control 12 ADC12MCTL12 1Ch
ADC memory control 13 ADC12MCTL13 1Dh
ADC memory control 14 ADC12MCTL14 1Eh
ADC memory control 15 ADC12MCTL15 1Fh
Conversion memory 0 ADC12MEM0 20h
Conversion memory 1 ADC12MEM1 22h
Conversion memory 2 ADC12MEM2 24h
Conversion memory 3 ADC12MEM3 26h
Conversion memory 4 ADC12MEM4 28h
Conversion memory 5 ADC12MEM5 2Ah
Conversion memory 6 ADC12MEM6 2Ch
Conversion memory 7 ADC12MEM7 2Eh
Conversion memory 8 ADC12MEM8 30h
Conversion memory 9 ADC12MEM9 32h
Conversion memory 10 ADC12MEM10 34h
Conversion memory 11 ADC12MEM11 36h
Conversion memory 12 ADC12MEM12 38h
Conversion memory 13 ADC12MEM13 3Ah
Conversion memory 14 ADC12MEM14 3Ch
Conversion memory 15 ADC12MEM15 3Eh

Table 6-49 DAC12_A Registers (Base Address: 0780h)

REGISTER DESCRIPTION REGISTER OFFSET
DAC12_A channel 0 control 0 DAC12_0CTL0 00h
DAC12_A channel 0 control 1 DAC12_0CTL1 02h
DAC12_A channel 0 data DAC12_0DAT 04h
DAC12_A channel 0 calibration control DAC12_0CALCTL 06h
DAC12_A channel 0 calibration data DAC12_0CALDAT 08h
DAC12_A channel 1 control 0 DAC12_1CTL0 10h
DAC12_A channel 1 control 1 DAC12_1CTL1 12h
DAC12_A channel 1 data DAC12_1DAT 14h
DAC12_A channel 1 calibration control DAC12_1CALCTL 16h
DAC12_A channel 1 calibration data DAC12_1CALDAT 18h
DAC12_A interrupt vector word DAC12IV 1Eh

Table 6-50 Comparator_B Registers (Base Address: 08C0h)

REGISTER DESCRIPTION REGISTER OFFSET
Comp_B control 0 CBCTL0 00h
Comp_B control 1 CBCTL1 02h
Comp_B control 2 CBCTL2 04h
Comp_B control 3 CBCTL3 06h
Comp_B interrupt CBINT 0Ch
Comp_B interrupt vector word CBIV 0Eh

Table 6-51 LDO and Port U Configuration Registers (Base Address: 0900h)

REGISTER DESCRIPTION REGISTER OFFSET
LDO key/ID LDOKEYID 00h
PU port control PUCTL 04h
LDO power control LDOPWRCTL 08h

Table 6-52 LCD_B Registers (Base Address: 0A00h)

REGISTER DESCRIPTION REGISTER OFFSET
LCD_B control 0 LCDBCTL0 000h
LCD_B control 1 LCDBCTL1 002h
LCD_B blinking control LCDBBLKCTL 004h
LCD_B memory control LCDBMEMCTL 006h
LCD_B voltage control LCDBVCTL 008h
LCD_B port control 0 LCDBPCTL0 00Ah
LCD_B port control 1 LCDBPCTL1 00Ch
LCD_B port control 2 LCDBPCTL2 00Eh
LCD_B charge pump control LCDBCTL0 012h
LCD_B interrupt vector word LCDBIV 01Eh
LCD_B memory 1 LCDM1 020h
LCD_B memory 2 LCDM2 021h
   ⋮    ⋮    ⋮
LCD_B memory 22 LCDM22 035h
LCD_B blinking memory 1 LCDBM1 040h
LCD_B blinking memory 2 LCDBM2 041h
   ⋮    ⋮    ⋮
LCD_B blinking memory 22 LCDBM22 055h

6.14 Input/Output Schematics

6.14.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger

Figure 6-2 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas566-020.gif Figure 6-2 Port P1 (P1.0 to P1.7) Schematic

Port P1 (P1.0 to P1.7) Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P1DIR.x P1SEL.x LCDS32...39
P1.0/TA0CLK/ACLK/ S39 0 P1.0 (I/O) I: 0; O: 1 0 0
Timer TA0.TA0CLK 0 1 0
ACLK 1 1 0
S39 X X 1
P1.1/TA0.0/S38 1 P1.1 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI0A capture input 0 1 0
Timer TA0.0 output 1 1 0
S38 X X 1
P1.2/TA0.1/S37 2 P1.2 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI1A capture input 0 1 0
Timer TA0.1 output 1 1 0
S37 X X 1
P1.3/TA0.2/S36 3 P1.3 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI2A capture input 0 1 0
Timer TA0.2 output 1 1 0
S36 X X 1
P1.4/TA0.3/S35 4 P1.4 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI3A capture input 0 1 0
Timer TA0.3 output 1 1 0
S35 X X 1
P1.5/TA0.4/S34 5 P1.5 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI4A capture input 0 1 0
Timer TA0.4 output 1 1 0
S34 X X 1
P1.6/TA0.1/S33 6 P1.6 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI1B capture input 0 1 0
Timer TA0.1 output 1 1 0
S33 X X 1
P1.7/TA0.2/S32 7 P1.7 (I/O) I: 0; O: 1 0 0
Timer TA0.CCI2B capture input 0 1 0
Timer TA0.2 output 1 1 0
S32 X X 1
(1) X = Don't care

6.14.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger

Figure 6-3 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas566-021.gif Figure 6-3 Port P2 (P2.0 to P2.7) Schematic

Port P2 (P2.0 to P2.7) Pin Functions

PIN NAME (P2.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P2DIR.x P2SEL.x P2MAPx
P2.0/P2MAP0 0 P2.0 (I/O) I: 0; O: 1 0
Mapped secondary digital function X 1 ≤ 19
P2.1/P2MAP1 1 P2.1 (I/O) I: 0; O: 1 0
Mapped secondary digital function X 1 ≤ 19
P2.2/P2MAP2 2 P2.2 (I/O) I: 0; O: 1 0
Mapped secondary digital function X 1 ≤ 19
P2.3/P2MAP3 3 P2.3 (I/O) I: 0; O: 1 0
Mapped secondary digital function X 1 ≤ 19
P2.4/P2MAP4 4 P2.4 (I/O) I: 0; O: 1 0
Mapped secondary digital function X 1 ≤ 19
P2.5/P2MAP5 5 P2.5 (I/O I: 0; O: 1 0
Mapped secondary digital function X 1 ≤ 19
P2.6/P2MAP6/R03 6 P2.6 (I/O) I: 0; O: 1 0
Mapped secondary digital function X 1 ≤ 19
R03 X 1 = 31
P2.7/P2MAP7/ LCDREF/R13 7 P2.7 (I/O) I: 0; O: 1 0
Mapped secondary digital function X 1 ≤ 19
LCDREF/R13 X 1 = 31

6.14.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger

Figure 6-4 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas566-022.gif Figure 6-4 Port P3 (P3.0 to P3.7) Schematic

Port P3 (P3.0 to P3.7) Pin Functions

PIN NAME (P3.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P3DIR.x P3SEL.x LCDS24...31
P3.0/TA1CLK/CBOUT/S31 0 P3.0 (I/O) I: 0; O: 1 0 0
Timer TA1.TA1CLK 0 1 0
CBOUT 1 1 0
S31 X X 1
P3.1/TA1.0/S30 1 P3.1 (I/O) I: 0; O: 1 0 0
Timer TA1.CCI0A capture input 0 1 0
Timer TA1.0 output 1 1 0
S30 X X 1
P3.2/TA1.1/S29 2 P3.2 (I/O) I: 0; O: 1 0 0
Timer TA1.CCI1A capture input 0 1 0
Timer TA1.1 output 1 1 0
S29 X X 1
P3.3/TA1.2/S28 3 P3.3 (I/O) I: 0; O: 1 0 0
Timer TA1.CCI2A capture input 0 1 0
Timer TA1.2 output 1 1 0
S28 X X 1
P3.4/TA2CLK/SMCLK/S27 4 P3.4 (I/O) I: 0; O: 1 0 0
Timer TA2.TA2CLK 0 1 0
SMCLK 1 1 0
S27 X X 1
P3.5/TA2.0/S26 5 P3.5 (I/O) I: 0; O: 1 0 0
Timer TA2.CCI0A capture input 0 1 0
Timer TA2.0 output 1 1 0
S26 X X 1
P3.6/TA2.1/S25 6 P3.6 (I/O) I: 0; O: 1 0 0
Timer TA2.CCI1A capture input 0 1 0
Timer TA2.1 output 1 1 1
S25 X X 1
P3.7/TA2.2/S24 7 P3.7 (I/O) I: 0; O: 1 0 0
Timer TA2.CCI2A capture input 0 1 0
Timer TA2.2 output 1 1 0
S24 X X 1

6.14.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger

Figure 6-5 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas566-023.gif Figure 6-5 Port P4 (P4.0 to P4.7) Schematic

Port P4 (P4.0 to P4.7) Pin Functions

PIN NAME (P4.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P4DIR.x P4SEL.x LCDS16...23
P4.0/TB0.0/S23 0 P4.0 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI0A capture input 0 1 0
Timer TB0.0 output(1) 1 1 0
S23 X X 1
P4.1/TB0.1/S22 1 P4.1 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI1A capture input 0 1 0
Timer TB0.1 output(1) 1 1 0
S22 X X 1
P4.2/TB0.2/S21 2 P4.2 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI2A capture input 0 1 0
Timer TB0.2 output(1) 1 1 0
S21 X X 1
P4.3/TB0.3/S20 3 P4.3 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI3A capture input 0 1 0
Timer TB0.3 output(1) 1 1 0
S20 X X 1
P4.4/TB0.4/S19 4 P4.4 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI4A capture input 0 1 0
Timer TB0.4 output(1) 1 1 0
S19 X X 1
P4.5/TB0.5/S18 5 P4.5 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI5A capture input 0 1 0
Timer TB0.5 output(1) 1 1 0
S18 X X 1
P4.6/TB0.6/S17 6 P4.6 (I/O) I: 0; O: 1 0 0
Timer TB0.CCI6A capture input 0 1 0
Timer TB0.6 output(1) 1 1 0
S17 X X 1
P4.7/TB0OUTH/ SVMOUT/S16 7 P4.7 (I/O) I: 0; O: 1 0 0
Timer TB0.TB0OUTH 0 1 0
SVMOUT 1 1 0
S16 X X 1
(1) Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance.

6.14.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger

Figure 6-6 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas566-024.gif Figure 6-6 Port P5 (P5.0 and P5.1) Schematic

Port P5 (P5.0 and P5.1) Pin Functions

PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P5DIR.x P5SEL.x REFOUT
P5.0/VREF+/VeREF+ 0 P5.0 (I/O)(1) I: 0; O: 1 0 X
VeREF+(2) X 1 0
VREF+(3) X 1 1
P5.1/VREF–/VeREF– 1 P5.1 (I/O)(1) I: 0; O: 1 0 X
VeREF–(4) X 1 0
VREF–(5) X 1 1
(1) Default condition
(2) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A, Comparator_B, or DAC12_A.
(3) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. The ADC12_A, VREF+ reference is available at the pin.
(4) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A, Comparator_B, or DAC12_A.
(5) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. The ADC12_A, VREF– reference is available at the pin.

6.14.6 Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger

Figure 6-7 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas566-027.gif Figure 6-7 Port P5 (P5.2 to P5.7) Schematic

Port P5 (P5.2 to P5.7) Pin Functions

PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P5DIR.x P5SEL.x LCDS40...42
P5.2/R23 2 P5.2 (I/O) I: 0; O: 1 0 N/A
R23 X 1 N/A
P5.3/COM1/S42 3 P5.3 (I/O) I: 0; O: 1 0 0
COM1 X 1 X
S42 X 0 1
P5.4/COM2/S41 4 P5.4 (I/O) I: 0; O: 1 0 0
COM2 X 1 X
S41 X 0 1
P5.5/COM3/S40 5 P5.5 (I/O) I: 0; O: 1 0 0
COM3 X 1 X
S40 X 0 1
P5.6/ADC12CLK/DMAE0 6 P5.6 (I/O) I: 0; O: 1 0 N/A
ADC12CLK 1 1 N/A
DMAE0 0 1 N/A
P5.7/RTCCLK 7 P5.7 (I/O) I: 0; O: 1 0 N/A
RTCCLK 1 1 N/A

6.14.7 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger

Figure 6-8 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas566-028.gif Figure 6-8 Port P6 (P6.0 to P6.7) Schematic

Port P6 (P6.0 to P6.7) Pin Functions

PIN NAME (P6.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P6DIR.x P6SEL.x CBPD.x DAC12OPS DAC12AMPx
P6.0/CB0/A0 0 P6.0 (I/O) I: 0; O: 1 0 0 N/A N/A
CB0 X X 1 N/A N/A
A0(1)(2) X 1 X N/A N/A
P6.1/CB1/A1 1 P6.1 (I/O) I: 0; O: 1 0 0 N/A N/A
CB1 X X 1 N/A N/A
A1(1)(2) X 1 X N/A N/A
P6.2/CB2/A2 2 P6.2 (I/O) I: 0; O: 1 0 0 N/A N/A
CB2 X X 1 N/A N/A
A2(1)(2) X 1 X N/A N/A
P6.3/CB3/A3 3 P6.3 (I/O) I: 0; O: 1 0 0 N/A N/A
CB3 X X 1 N/A N/A
A3(1)(2) X 1 X N/A N/A
P6.4/CB4/A4 4 P6.4 (I/O) I: 0; O: 1 0 0 N/A N/A
CB4 X X 1 N/A N/A
A4(1)(2) X 1 X N/A N/A
P6.5/CB5/A5 5 P6.5 (I/O) I: 0; O: 1 0 0 N/A N/A
CB5 X X 1 N/A N/A
A5(1)(2) X 1 X N/A N/A
P6.6/CB6/A6/DAC0 6 P6.6 (I/O) I: 0; O: 1 0 0 X 0
CB6 X X 1 X 0
A6(1)(2) X 1 X X 0
DAC0 X X X 0 >1
P6.7/CB7/A7/DAC1 7 P6.7 (I/O) I: 0; O: 1 0 0 X 0
CB7 X X 1 X 0
A7(1)(2) X 1 X X 0
DAC1 X X X 0 >1
(1) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.
(2) The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.

6.14.8 Port P7, P7.2, Input/Output With Schmitt Trigger

Figure 6-9 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas566-025.gif Figure 6-9 Port P7 (P7.2) Schematic

6.14.9 Port P7, P7.3, Input/Output With Schmitt Trigger

Figure 6-10 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas566-026.gif Figure 6-10 Port P7 (P7.3) Schematic

Port P7 (P7.2 and P7.3) Pin Functions

PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P7DIR.x P7SEL.2 P7SEL.3 XT2BYPASS
P7.2/XT2IN 2 P7.2 (I/O) I: 0; O: 1 0 X X
XT2IN crystal mode(1) X 1 X 0
XT2IN bypass mode(1) X 1 X 1
P7.3/XT2OUT 3 P7.3 (I/O) I: 0; O: 1 0 0 X
XT2OUT crystal mode(2) X 1 X 0
P7.3 (I/O)(2) X 1 0 1
(1) Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal mode or bypass mode.
(2) Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as general-purpose I/O.

6.14.10 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger

Figure 6-11 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas566-032.gif Figure 6-11 Port P7 (P7.4 to P7.7) Schematic

Port P7 (P7.4 to P7.7) Pin Functions

PIN NAME (P7.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P7DIR.x P7SEL.x CBPD.x DAC12OPS DAC12AMPx
P7.4/CB8/A12 4 P7.4 (I/O) I: 0; O: 1 0 0 N/A N/A
Comparator_B input CB8 X X 1 N/A N/A
A12(1)(2) X 1 X N/A N/A
P7.5/CB9/A13 5 P7.5 (I/O) I: 0; O: 1 0 0 N/A N/A
Comparator_B input CB9 X X 1 N/A N/A
A13(1)(2) X 1 X N/A N/A
P7.6/CB10/A14/DAC0 6 P7.6 (I/O) I: 0; O: 1 0 0 X 0
Comparator_B input CB10 X X 1 X 0
A14(1)(2) X 1 X X 0
DAC12_A output DAC0 X X X 1 >1
P7.7/CB11/A15/DAC1 7 P7.7 (I/O) I: 0; O: 1 0 0 X 0
A15(1)(2) X 1 X X 0
DAC12_A output DAC1 X X X 1 >1
(1) Setting the P7SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.
(2) The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.

6.14.11 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger

Figure 6-12 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas566-033.gif Figure 6-12 Port P8 (P8.0 to P8.7) Schematic

Port P8 (P8.0 to P8.7) Pin Functions

PIN NAME (P9.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P8DIR.x P8SEL.x LCDS8...15
P8.0/TB0CLK/S15 0 P8.0 (I/O) I: 0; O: 1 0 0
Timer TB0.TB0CLK clock input 0 1 0
S15 X X 1
P8.1/UCB1STE/UCA1CLK/S14 1 P8.1 (I/O) I: 0; O: 1 0 0
UCB1STE/UCA1CLK X 1 0
S14 X X 1
P8.2/UCA1TXD/UCA1SIMO/S13 2 P8.2 (I/O) I: 0; O: 1 0 0
UCA1TXD/UCA1SIMO X 1 0
S13 X X 1
P8.3/UCA1RXD/UCA1SOMI/S12 3 P8.3 (I/O) I: 0; O: 1 0 0
UCA1RXD/UCA1SOMI X 1 0
S12 X X 1
P8.4/UCB1CLK/UCA1STE/S11 4 P8.4 (I/O) I: 0; O: 1 0 0
UCB1CLK/UCA1STE X 1 0
S11 X X 1
P8.5/UCB1SIMO/UCB1SDA/S10 5 P8.5 (I/O) I: 0; O: 1 0 0
UCB1SIMO/UCB1SDA X 1 0
S10 X X 1
P8.6/UCB1SOMI/UCB1SCL/S9 6 P8.6 (I/O) I: 0; O: 1 0 0
UCB1SOMI/UCB1SCL X 1 0
S9 X X 1
P8.7/S8 7 P8.7 (I/O) I: 0; O: 1 0 0
S8 X X 1

6.14.12 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger

Figure 6-13 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas700-IOSchematicsP9.gif Figure 6-13 Port P9 (P9.0 to P9.7) Schematic

Port P9 (P9.0 to P9.7) Pin Functions

PIN NAME (P9.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P9DIR.x P9SEL.x LCDS0...7
P9.0/S7 0 P9.0 (I/O) I: 0; O: 1 0 0
S7 X X 1
P9.1/UCB2STE/UCA2CLK/S6 1 P9.1 (I/O) I: 0; O: 1 0 0
UCB2STE/UCA2CLK X 1 0
S6 X X 1
P9.2/UCA2TXD/UCA2SIMO/S5 2 P9.2 (I/O) I: 0; O: 1 0 0
UCA2TXD/UCA2SIMO X 1 0
S5 X X 1
P9.3/UCA2RXD/UCA2SOMI/S4 3 P9.3 (I/O) I: 0; O: 1 0 0
UCA2RXD/UCA2SOMI X 1 0
S4 X X 1
P9.4/UCB2CLK/UCA2STE/S3 4 P9.4 (I/O) I: 0; O: 1 0 0
UCB2CLK/UCA2STE X 1 0
S3 X X 1
P9.5/UCB2SIMO/UCB2SDA/S2 5 P9.5 (I/O) I: 0; O: 1 0 0
UCB2SIMO/UCB2SDA X 1 0
S2 X X 1
P9.6/UCB2SOMI/UCB2SCLK/S1 6 P9.6 (I/O) I: 0; O: 1 0 0
UCB2SOMI/UCB2SCLK X 1 0
S1 X X 1
P9.7/S0 7 P9.7 (I/O) I: 0; O: 1 0 0
S0 X X 1

6.14.13 Port PU.0, PU.1 Ports

Figure 6-14 shows the port schematic. Table 6-53 summarizes selection of the pin function.

MSP430F6459-HIREL slas678-pu.gif Figure 6-14 Port U (PU.0 and PU.1) Schematic

Table 6-53 Port PU.0, PU.1 Functions(1)

PUIPE PUOPE PUOUT1 PUOUT0 PU.1 PU.0 PORT U FUNCTION
0 1 0 0 Output low Output low Outputs enabled
0 1 0 1 Output low Output high Outputs enabled
0 1 1 0 Output high Output low Outputs enabled
0 1 1 1 Output high Output high Outputs enabled
1 0 X X Input enabled Input enabled Inputs enabled
0 0 X X Hi-Z Hi-Z Outputs and inputs disabled
(1) PU.1 and PU.0 inputs and outputs are supplied from LDOO. LDOO can be generated by the device using the integrated 3.3-V LDO when enabled. LDOO can also be supplied externally when the 3.3-V LDO is not being used and is disabled.

6.14.14 Port J, PJ.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output

Figure 6-15 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas566-037.gif Figure 6-15 Port PJ (PJ.0) Schematic

6.14.15 Port J, PJ.1 to PJ.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output

Figure 6-16 shows the port schematic. summarizes selection of the pin function.

MSP430F6459-HIREL slas566-038.gif Figure 6-16 Port PJ (PJ.1 to PJ.3) Schematic

Port PJ (PJ.0 to PJ.3) Pin Functions

PIN NAME (PJ.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
PJDIR.x
PJ.0/TDO 0 PJ.0 (I/O)(1) I: 0; O: 1
TDO(2) X
PJ.1/TDI/TCLK 1 PJ.1 (I/O)(1) I: 0; O: 1
TDI/TCLK(2) (3) X
PJ.2/TMS 2 PJ.2 (I/O)(1) I: 0; O: 1
TMS(2) (3) X
PJ.3/TCK 3 PJ.3 (I/O)(1) I: 0; O: 1
TCK(2) (3) X
(1) Default condition
(2) The pin direction is controlled by the JTAG module.
(3) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.

6.15 Device Descriptors

Table 6-54 lists the contents of the device descriptor tag-length-value (TLV) structure for each device type.

Table 6-54 Device Descriptor Table(1)

DESCRIPTION ADDRESS SIZE
(bytes)
VALUE
F6659 F6658 F6459 F6458 F5659 F5658 F5359 F5358
Info Block Info length 01A00h 1 06h 06h 06h 06h 06h 06h 06h 06h
CRC length 01A01h 1 06h 06h 06h 06h 06h 06h 06h 06h
CRC value 01A02h 2 per unit per unit per unit per unit per unit per unit per unit per unit
Device ID 01A04h 2 812Bh 812Ch 812Dh 812Eh 8130h 8131h 8132h 8133h
Hardware revision 01A06h 1 10h 10h 10h 10h 10h 10h 10h 10h
Firmware revision 01A07h 1 10h 10h 10h 10h 10h 10h 10h 10h
Die Record Die record tag 01A08h 1 08h 08h 08h 08h 08h 08h 08h 08h
Die record length 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah
Lot/wafer ID 01A0Ah 4 per unit per unit per unit per unit per unit per unit per unit per unit
Die X position 01A0Eh 2 per unit per unit per unit per unit per unit per unit per unit per unit
Die Y position 01A10h 2 per unit per unit per unit per unit per unit per unit per unit per unit
Test results 01A12h 2 per unit per unit per unit per unit per unit per unit per unit per unit
ADC12 Calibration ADC12 calibration tag 01A14h 1 11h 11h 11h 11h 11h 11h 11h 11h
ADC12 calibration length 01A15h 1 10h 10h 10h 10h 10h 10h 10h 10h
ADC gain factor 01A16h 2 per unit per unit per unit per unit per unit per unit per unit per unit
ADC offset 01A18h 2 per unit per unit per unit per unit per unit per unit per unit per unit
ADC 1.5-V reference
temperature sensor 30°C
01A1Ah 2 per unit per unit per unit per unit per unit per unit per unit per unit
ADC 1.5-V reference
temperature sensor 105°C
01A1Ch 2 per unit per unit per unit per unit per unit per unit per unit per unit
ADC 2.0-V reference
temperature sensor 30°C
01A1Eh 2 per unit per unit per unit per unit per unit per unit per unit per unit
ADC 2.0-V reference
temperature sensor 105°C
01A20h 2 per unit per unit per unit per unit per unit per unit per unit per unit
ADC 2.5-V reference
temperature sensor 30°C
01A22h 2 per unit per unit per unit per unit per unit per unit per unit per unit
ADC 2.5-V reference
temperature sensor 105°C
01A24h 2 per unit per unit per unit per unit per unit per unit per unit per unit
REF Calibration REF calibration tag 01A26h 1 12h 12h 12h 12h 12h 12h 12h 12h
REF calibration length 01A27h 1 06h 06h 06h 06h 06h 06h 06h 06h
REF 1.5-V
reference factor
01A28h 2 per unit per unit per unit per unit per unit per unit per unit per unit
REF 2.0-V
reference factor
01A2Ah 2 per unit per unit per unit per unit per unit per unit per unit per unit
REF 2.5-V
reference factor
01A2Ch 2 per unit per unit per unit per unit per unit per unit per unit per unit
(1) N/A = Not applicable