SLASEC3A August   2016  – August 2016 MSP430F6459-HIREL

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Schmitt-Trigger Inputs - General-Purpose I/O
    8. 5.8  Leakage Current - General-Purpose I/O
    9. 5.9  Outputs - General-Purpose I/O (Full Drive Strength)
    10. 5.10 Outputs - General-Purpose I/O (Reduced Drive Strength)
    11. 5.11 Thermal Resistance Characteristics for PZ Package
    12. 5.12 Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    13. 5.13 Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    14. 5.14 Timing and Switching Characteristics
      1. 5.14.1 Power Supply Sequencing
      2. 5.14.2 Clock Specifications
      3. 5.14.3 Peripherals
      4. 5.14.4 Emulation and Debug
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Instruction Set
    4. 6.4  Operating Modes
    5. 6.5  Interrupt Vector Addresses
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
      1. 6.7.1 UART BSL
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire Interface
    9. 6.9  Flash Memory
    10. 6.10 Memory Integrity Detection (MID)
    11. 6.11 RAM
    12. 6.12 Backup RAM
    13. 6.13 Peripherals
      1. 6.13.1  Digital I/O
      2. 6.13.2  Port Mapping Controller
      3. 6.13.3  Oscillator and System Clock
      4. 6.13.4  Power-Management Module (PMM)
      5. 6.13.5  Hardware Multiplier (MPY)
      6. 6.13.6  Real-Time Clock (RTC_B)
      7. 6.13.7  Watchdog Timer (WDT_A)
      8. 6.13.8  System Module (SYS)
      9. 6.13.9  DMA Controller
      10. 6.13.10 Universal Serial Communication Interface (USCI)
      11. 6.13.11 Timer TA0
      12. 6.13.12 Timer TA1
      13. 6.13.13 Timer TA2
      14. 6.13.14 Timer TB0
      15. 6.13.15 Comparator_B
      16. 6.13.16 ADC12_A
      17. 6.13.17 DAC12_A
      18. 6.13.18 CRC16
      19. 6.13.19 Voltage Reference (REF) Module
      20. 6.13.20 LCD_B
      21. 6.13.21 LDO and PU Port
      22. 6.13.22 Embedded Emulation Module (EEM) (L Version)
      23. 6.13.23 Peripheral File Map
    14. 6.14 Input/Output Schematics
      1. 6.14.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.14.2  Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 6.14.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
      4. 6.14.4  Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 6.14.5  Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 6.14.6  Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger
      7. 6.14.7  Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      8. 6.14.8  Port P7, P7.2, Input/Output With Schmitt Trigger
      9. 6.14.9  Port P7, P7.3, Input/Output With Schmitt Trigger
      10. 6.14.10 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      11. 6.14.11 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      12. 6.14.12 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      13. 6.14.13 Port PU.0, PU.1 Ports
      14. 6.14.14 Port J, PJ.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 6.14.15 Port J, PJ.1 to PJ.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    15. 6.15 Device Descriptors
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 General Layout Recommendations
      6. 7.1.6 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
      1. 8.3.1 Hardware Features
      2. 8.3.2 Recommended Hardware Options
        1. 8.3.2.1 Target Socket Boards
        2. 8.3.2.2 Experimenter Boards
        3. 8.3.2.3 Debugging and Programming Tools
        4. 8.3.2.4 Production Programmers
      3. 8.3.3 Recommended Software Options
        1. 8.3.3.1 Integrated Development Environments
        2. 8.3.3.2 MSP430Ware
        3. 8.3.3.3 TI-RTOS
        4. 8.3.3.4 Command-Line Programmer
    4. 8.4  Documentation Support
    5. 8.5  Receiving Notification of Documentation Updates
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the pinout diagram.

MSP430F6459-HIREL po-f6459-slasec3.gif Figure 4-1 PZ S-PQFP-G100 Package

4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1 Signal Descriptions

TERMINAL I/O(1) DESCRIPTION
NAME NO.
P6.4/CB4/A4 1 I/O General-purpose digital I/O

Comparator_B input CB4

Analog input A4 – ADC

P6.5/CB5/A5 2 I/O General-purpose digital I/O

Comparator_B input CB5

Analog input A5 – ADC

P6.6/CB6/A6/DAC0 3 I/O General-purpose digital I/O

Comparator_B input CB6

Analog input A6 – ADC

DAC12.0 output

P6.7/CB7/A7/DAC1 4 I/O General-purpose digital I/O

Comparator_B input CB7

Analog input A7 – ADC

DAC12.1 output

P7.4/CB8/A12 5 I/O General-purpose digital I/O

Comparator_B input CB8

Analog input A12 –ADC

P7.5/CB9/A13 6 I/O General-purpose digital I/O

Comparator_B input CB9

Analog input A13 – ADC

P7.6/CB10/A14/DAC0 7 I/O General-purpose digital I/O

Comparator_B input CB10

Analog input A14 – ADC

DAC12.0 output

P7.7/CB11/A15/DAC1 8 I/O General-purpose digital I/O

Comparator_B input CB11

Analog input A15 – ADC

DAC12.1 output

P5.0/VREF+/VeREF+ 9 I/O General-purpose digital I/O

Output of reference voltage to the ADC

Input for an external reference voltage to the ADC
P5.1/VREF-/VeREF- 10 I/O General-purpose digital I/O

Negative terminal for the ADC's reference voltage for both sources, the internal reference voltage, or an external applied reference voltage
AVCC1 11 Analog power supply
AVSS1 12 Analog ground supply
XIN 13 I Input terminal for crystal oscillator XT1
XOUT 14 O Output terminal of crystal oscillator XT1
AVSS2 15 Analog ground supply
P5.6/ADC12CLK/DMAE0 16 I/O General-purpose digital I/O

Conversion clock output ADC

DMA external trigger input
P2.0/P2MAP0 17 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output
P2.1/P2MAP1 18 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave in, master out; USCI_B0 I2C data

P2.2/P2MAP2 19 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave out, master in; USCI_B0 I2C clock
P2.3/P2MAP3 20 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
P2.4/P2MAP4 21 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in, master out
P2.5/P2MAP5 22 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART receive data; USCI_A0 slave out, master in
P2.6/P2MAP6/R03 23 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: no secondary function

Input/output port of lowest analog LCD voltage (V5)
P2.7/P2MAP7/LCDREF/R13 24 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: no secondary function

External reference voltage input for regulated LCD voltage

Input/output port of third most positive analog LCD voltage (V3 or V4)
DVCC1 25 Digital power supply
DVSS1 26 Digital ground supply
VCORE(2) 27 Regulated core power supply (internal use only, no external current loading)
P5.2/R23 28 I/O General-purpose digital I/O

Input/output port of second most positive analog LCD voltage (V2)
LCDCAP/R33 29 I/O LCD capacitor connection

Input/output port of most positive analog LCD voltage (V1)
COM0 30 O LCD common output COM0 for LCD backplane
P5.3/COM1/S42 31 I/O General-purpose digital I/O

LCD common output COM1 for LCD backplane

LCD segment output S42
P5.4/COM2/S41 32 I/O General-purpose digital I/O

LCD common output COM2 for LCD backplane

LCD segment output S41
P5.5/COM3/S40 33 I/O General-purpose digital I/O

LCD common output COM3 for LCD backplane

LCD segment output S40
P1.0/TA0CLK/ACLK/S39 34 I/O General-purpose digital I/O with port interrupt

Timer TA0 clock signal TACLK input

ACLK output (divided by 1, 2, 4, 8, 16, or 32)

LCD segment output S39
P1.1/TA0.0/S38 35 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output

LCD segment output S38
P1.2/TA0.1/S37 36 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input

LCD segment output S37
P1.3/TA0.2/S36 37 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output

LCD segment output S36
P1.4/TA0.3/S35 38 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR3 capture: CCI3A input compare: Out3 output

LCD segment output S35
P1.5/TA0.4/S34 39 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output

LCD segment output S34
P1.6/TA0.1/S33 40 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output

LCD segment output S33
P1.7/TA0.2/S32 41 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output

LCD segment output S32
P3.0/TA1CLK/CBOUT/S31 42 I/O General-purpose digital I/O with port interrupt

Timer TA1 clock input

Comparator_B output

LCD segment output S31
P3.1/TA1.0/S30 43 I/O General-purpose digital I/O with port interrupt

Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

LCD segment output S30
P3.2/TA1.1/S29 44 I/O General-purpose digital I/O with port interrupt

Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

LCD segment output S29
P3.3/TA1.2/S28 45 I/O General-purpose digital I/O with port interrupt

Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

LCD segment output S28
P3.4/TA2CLK/SMCLK/S27 46 I/O General-purpose digital I/O with port interrupt

Timer TA2 clock input

SMCLK output

LCD segment output S27
P3.5/TA2.0/S26 47 I/O General-purpose digital I/O with port interrupt

Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

LCD segment output S26
P3.6/TA2.1/S25 48 I/O General-purpose digital I/O with port interrupt

Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

LCD segment output S25
P3.7/TA2.2/S24 49 I/O General-purpose digital I/O with port interrupt

Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

LCD segment output S24
P4.0/TB0.0/S23 50 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

LCD segment output S23
P4.1/TB0.1/S22 51 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

LCD segment output S22
P4.2/TB0.2/S21 52 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

LCD segment output S21
P4.3/TB0.3/S20 53 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output

LCD segment output S20
P4.4/TB0.4/S19 54 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output

LCD segment output S19
P4.5/TB0.5/S18 55 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output

LCD segment output S18
P4.6/TB0.6/S17 56 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output

LCD segment output S17
P4.7/TB0OUTH/SVMOUT/S16 57 I/O General-purpose digital I/O with port interrupt

Timer TB0: Switch all PWM outputs high impedance

SVM output

LCD segment output S16
P8.0/TB0CLK/S15 58 I/O General-purpose digital I/O

Timer TB0 clock input

LCD segment output S15
P8.1/UCB1STE/UCA1CLK/S14 59 I/O General-purpose digital I/O

USCI_B1 SPI slave transmit enable

USCI_A1 clock input/output

LCD segment output S14
P8.2/UCA1TXD/UCA1SIMO/S13 60 I/O General-purpose digital I/O

USCI_A1 UART transmit data

USCI_A1 SPI slave in, master out

LCD segment output S13
P8.3/UCA1RXD/UCA1SOMI/S12 61 I/O General-purpose digital I/O

USCI_A1 UART receive data

USCI_A1 SPI slave out, master in

LCD segment output S12
P8.4/UCB1CLK/UCA1STE/S11 62 I/O General-purpose digital I/O

USCI_B1 clock input/output

USCI_A1 SPI slave transmit enable

LCD segment output S11
DVSS2 63 Digital ground supply
DVCC2 64 Digital power supply
P8.5/UCB1SIMO/UCB1SDA/S10 65 I/O General-purpose digital I/O

USCI_B1 SPI slave in, master out

USCI_B1 I2C data

LCD segment output S10
P8.6/UCB1SOMI/UCB1SCL/S9 66 I/O General-purpose digital I/O

USCI_B1 SPI slave out, master in

USCI_B1 I2C clock

LCD segment output S9
P8.7/S8 67 I/O General-purpose digital I/O

LCD segment output S8
P9.0/S7 68 I/O General-purpose digital I/O

LCD segment output S7
P9.1/UCB2STE/UCA2CLK/S6 69 I/O General-purpose digital I/O

USCI_B2 SPI slave transmit enable

USCI_A2 clock input/output

LCD segment output S6
P9.2/UCA2TXD/UCA2SIMO/S5 70 I/O General-purpose digital I/O

USCI_A2 UART transmit data

USCI_A2 SPI slave in, master out

LCD segment output S5
P9.3/UCA2RXD/UCA2SOMI/S4 71 I/O General-purpose digital I/O

USCI_A2 UART receive data

USCI_A2 SPI slave out, master in

LCD segment output S4
P9.4/UCB2CLK/UCA2STE/S3 72 I/O General-purpose digital I/O

USCI_B2 clock input/output

USCI_A2 SPI slave transmit enable

LCD segment output S3
P9.5/UCB2SIMO/UCB2SDA/S2 73 I/O General-purpose digital I/O

USCI_B2 SPI slave in, master out

USCI_B2 I2C data

LCD segment output S2
P9.6/UCB2SOMI/UCB2SCL/S1 74 I/O General-purpose digital I/O

USCI_B2 SPI slave out, master in

USCI_B2 I2C clock

LCD segment output S1
P9.7/S0 75 I/O General-purpose digital I/O

LCD segment output S0
VSSU 76 PU ground supply
PU.0/DP 77 I/O PU control register (Port U is supplied the LDOO rail)
NC 78 Not connected
PU.1/DM 79 I/O PU control register (Port U is supplied the LDOO rail)
LDOI 80 LDO input
LDOO 81 LDO output
NC 82 Not connected
AVSS3 83 Analog ground supply
P7.2/XT2IN 84 I/O General-purpose digital I/O

Input terminal for crystal oscillator XT2
P7.3/XT2OUT 85 I/O General-purpose digital I/O

Output terminal of crystal oscillator XT2
VBAK 86 Capacitor for backup subsystem. Do not load this pin externally. For capacitor values, see CBAK in Section 5.3.
VBAT 87 Backup supply voltage. If backup voltage is not supplied, connect to DVCC externally.
P5.7/RTCCLK 88 I/O General-purpose digital I/O

RTCCLK output
DVCC3 89 Digital power supply
DVSS3 90 Digital ground supply
TEST/SBWTCK 91 I Test mode pin – select digital I/O on JTAG pins

Spy-Bi-Wire input clock
PJ.0/TDO 92 I/O General-purpose digital I/O

Test data output port
PJ.1/TDI/TCLK 93 I/O General-purpose digital I/O

Test data input or test clock input
PJ.2/TMS 94 I/O General-purpose digital I/O

Test mode select
PJ.3/TCK 95 I/O General-purpose digital I/O

Test clock
RST/NMI/SBWTDIO 96 I/O Reset input active low(3)

Nonmaskable interrupt input

Spy-Bi-Wire data input/output
P6.0/CB0/A0 97 I/O General-purpose digital I/O

Comparator_B input CB0

Analog input A0 – ADC

P6.1/CB1/A1 98 I/O General-purpose digital I/O

Comparator_B input CB1

Analog input A1 – ADC

P6.2/CB2/A2 99 I/O General-purpose digital I/O

Comparator_B input CB2

Analog input A2 – ADC

P6.3/CB3/A3 100 I/O General-purpose digital I/O

Comparator_B input CB3

Analog input A3 – ADC

Reserved N/A

Reserved BGA package balls. TI recommends connecting to ground (DVSS, AVSS).
(1) I = input, O = output, N/A = not available on this package offering.
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE.
(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.