SLAS731D December   2011  – September 2018 MSP430F6720 , MSP430F6721 , MSP430F6723 , MSP430F6724 , MSP430F6725 , MSP430F6726 , MSP430F6730 , MSP430F6731 , MSP430F6733 , MSP430F6734 , MSP430F6735 , MSP430F6736

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-3 Terminal Functions, PZ Package
      2. Table 4-4 Terminal Functions, PN Package
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Thermal Resistance Characteristics
    8. 5.8  Digital I/O Ports
      1. Table 5-1 Schmitt-Trigger Inputs – General-Purpose I/O
      2. Table 5-2 Inputs – Ports P1 and P2
      3. Table 5-3 Leakage Current – General-Purpose I/O
      4. Table 5-4 Outputs – General-Purpose I/O (Full Drive Strength)
      5. Table 5-5 Typical Characteristics – General-Purpose I/O (Full Drive Strength)
      6. Table 5-6 Outputs – General-Purpose I/O (Reduced Drive Strength)
      7. 5.8.1     Typical Characteristics – General-Purpose I/O (Reduced Drive Strength)
      8. Table 5-7 Output Frequency – General-Purpose I/O
    9. 5.9  Clock Specifications
      1. Table 5-8  Crystal Oscillator, XT1, Low-Frequency Mode
      2. Table 5-9  Internal Very-Low-Power Low-Frequency Oscillator (VLO)
      3. Table 5-10 Internal Reference, Low-Frequency Oscillator (REFO)
      4. Table 5-11 DCO Frequency
    10. 5.10 Power-Management Module (PMM)
      1. Table 5-12 PMM, Brownout Reset (BOR)
      2. Table 5-13 PMM, Core Voltage
      3. Table 5-14 PMM, SVS High Side
      4. Table 5-15 PMM, SVM High Side
      5. Table 5-16 PMM, SVS Low Side
      6. Table 5-17 PMM, SVM Low Side
      7. Table 5-18 Wake-up Times From Low-Power Modes and Reset
    11. 5.11 Auxiliary Supplies
      1. Table 5-19 Auxiliary Supplies, Recommended Operating Conditions
      2. Table 5-20 Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents
      3. Table 5-21 Auxiliary Supplies, Auxiliary Supply Monitor
      4. Table 5-22 Auxiliary Supplies, Switch ON-Resistance
      5. Table 5-23 Auxiliary Supplies, Switching Time
      6. Table 5-24 Auxiliary Supplies, Switch Leakage
      7. Table 5-25 Auxiliary Supplies, Auxiliary Supplies to ADC10_A
      8. Table 5-26 Auxiliary Supplies, Charge Limiting Resistor
    12. 5.12 Timer_A
      1. Table 5-27 Timer_A
    13. 5.13 eUSCI
      1. Table 5-28 eUSCI (UART Mode) Clock Frequency
      2. Table 5-29 eUSCI (UART Mode) Switching Characteristics
      3. Table 5-30 eUSCI (SPI Master Mode) Clock Frequency
      4. Table 5-31 eUSCI (SPI Master Mode) Switching Characteristics
      5. Table 5-32 eUSCI (SPI Slave Mode)
      6. Table 5-33 eUSCI (I2C Mode)
    14. 5.14 LCD Controller
      1. Table 5-34 LCD_C Recommended Operating Conditions
      2. Table 5-35 LCD_C Electrical Characteristics
    15. 5.15 SD24_B
      1. Table 5-36 SD24_B Power Supply and Recommended Operating Conditions
      2. Table 5-37 SD24_B Analog Input
      3. Table 5-38 SD24_B Supply Currents
      4. Table 5-39 SD24_B Performance
      5. Table 5-40 SD24_B AC Performance
      6. Table 5-41 SD24_B AC Performance
      7. Table 5-42 SD24_B AC Performance
      8. Table 5-43 SD24_B External Reference Input
    16. 5.16 ADC10_A
      1. Table 5-44 10-Bit ADC, Power Supply and Input Range Conditions
      2. Table 5-45 10-Bit ADC, Timing Parameters
      3. Table 5-46 10-Bit ADC, Linearity Parameters
      4. Table 5-47 10-Bit ADC, External Reference
    17. 5.17 REF
      1. Table 5-48 REF, Built-In Reference
    18. 5.18 Flash Memory
      1. Table 5-49 Flash Memory
    19. 5.19 Emulation and Debug
      1. Table 5-50 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  Flash Memory
    9. 6.9  RAM
    10. 6.10 Backup RAM
    11. 6.11 Peripherals
      1. 6.11.1  Oscillator and System Clock
      2. 6.11.2  Power Management Module (PMM)
      3. 6.11.3  Auxiliary Supply System
      4. 6.11.4  Backup Subsystem
      5. 6.11.5  Digital I/O
      6. 6.11.6  Port Mapping Controller
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  Watchdog Timer (WDT_A)
      9. 6.11.9  DMA Controller
      10. 6.11.10 CRC16
      11. 6.11.11 Hardware Multiplier
      12. 6.11.12 Enhanced Universal Serial Communication Interface (eUSCI)
      13. 6.11.13 ADC10_A
      14. 6.11.14 SD24_B
      15. 6.11.15 TA0
      16. 6.11.16 TA1
      17. 6.11.17 TA2
      18. 6.11.18 TA3
      19. 6.11.19 SD24_B Triggers
      20. 6.11.20 ADC10_A Triggers
      21. 6.11.21 Real-Time Clock (RTC_C)
      22. 6.11.22 Reference (REF) Module Voltage Reference
      23. 6.11.23 LCD_C
      24. 6.11.24 Embedded Emulation Module (EEM) (S Version)
      25. 6.11.25 Peripheral File Map
    12. 6.12 Input/Output Diagrams
      1. 6.12.1  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN)
      2. 6.12.2  Port P1 (P1.2) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN)
      3. 6.12.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN)
      4. 6.12.4  Port P1 (P1.6 and P1.7) (MSP430F67xxIPZ and MSP430F67xxIPN), Port P2 (P2.0 and P2.1) (MSP430F67xxIPZ Only) Input/Output With Schmitt Trigger
      5. 6.12.5  Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      6. 6.12.6  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      7. 6.12.7  Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      8. 6.12.8  Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      9. 6.12.9  Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      10. 6.12.10 Port P9 (P9.0) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      11. 6.12.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      12. 6.12.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
      13. 6.12.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
      14. 6.12.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
      15. 6.12.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
      16. 6.12.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      17. 6.12.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    13. 6.13 Device Descriptors (TLV)
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.11.6 Port Mapping Controller

The port mapping controller allows flexible and reconfigurable mapping of digital functions to P1, P2, and P3 (see Table 6-9). Table 6-10 lists the default settings for all pins that support port mapping.

Table 6-9 Port Mapping Mnemonics and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
1 PM_UCA0RXD eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
PM_UCA0SOMI eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
2 PM_UCA0TXD eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
PM_UCA0SIMO eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
3 PM_UCA0CLK eUSCI_A0 clock input/output (direction controlled by eUSCI)
4 PM_UCA0STE eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI)
5 PM_UCA1RXD eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
PM_UCA1SOMI eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
6 PM_UCA1TXD eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
PM_UCA1SIMO eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
7 PM_UCA1CLK eUSCI_A1 clock input/output (direction controlled by eUSCI)
8 PM_UCA1STE eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
9 PM_UCA2RXD eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
PM_UCA2SOMI eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
10 PM_UCA2TXD eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
PM_ UCA2SIMO eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
11 PM_UCA2CLK eUSCI_A2 clock input/output (direction controlled by eUSCI)
12 PM_UCA2STE eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
13 PM_UCB0SIMO eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
PM_UCB0SDA eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
14 PM_UCB0SOMI eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
PM_UCB0SCL eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
15 PM_UCB0CLK eUSCI_B0 clock input/output (direction controlled by eUSCI)
16 PM_UCB0STE eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI)
17 PM_TA0.0 TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
18 PM_TA0.1 TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
19 PM_TA0.2 TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
20 PM_TA1.0 TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0
21 PM_TA1.1 TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
22 PM_TA2.0 TA2 CCR0 capture input CCI0A TA2 CCR0 compare output Out0
23 PM_TA2.1 TA2 CCR1 capture input CCI1A TA2 CCR1 compare output Out1
24 PM_TA3.0 TA3 CCR0 capture input CCI0A TA3 CCR0 compare output Out0
25 PM_TA3.1 TA3 CCR1 capture input CCI1A TA3 CCR1 compare output Out1
26 PM_TACLK Timer_A clock input to
TA0, TA1, TA2, TA3		 None
PM_RTCCLK None RTC_C clock output
27 PM_SDCLK SD24_B bitstream clock input/output (direction controlled by SD24_B)
28 PM_SD0DIO SD24_B converter-0 bitstream data input/output (direction controlled by SD24_B)
29 PM_SD1DIO SD24_B converter-1 bitstream data input/output (direction controlled by SD24_B)
30 PM_SD2DIO SD24_B converter-2 bitstream data input/output (direction controlled by SD24_B)
31 (0FFh)(1) PM_ANALOG Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are ignored, which results in a read value of 31.

Table 6-10 Default Mapping

PIN NAME PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
PZ PN
P1.0/PM_TA0.0/
VeREF-/A2		 P1.0/PM_TA0.0/
VeREF-/A2		 PM_TA0.0 TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
P1.1/PM_TA0.1/
VeREF+/A1		 P1.1/PM_TA0.1/
VeREF+/A1		 PM_TA0.1 TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0		 P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0		 PM_UCA0RXD,
PM_UCA0SOMI		 eUSCI_A0 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A0 SPI slave out master in
(direction controlled by eUSCI)
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03		 P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03		 PM_UCA0TXD,
PM_UCA0SIMO		 eUSCI_A0 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A0 SPI slave in master out
(direction controlled by eUSCI)
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13		 P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13		 PM_UCA1RXD,
PM_UCA1SOMI		 eUSCI_A1 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A1 SPI slave out master in
(direction controlled by eUSCI)
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23		 P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23		 PM_UCA1TXD,
PM_UCA1SIMO		 eUSCI_A1 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A1 SPI slave in master out
(direction controlled by eUSCI)
P1.6/PM_UCA0CLK/
COM4		 P1.6/PM_UCA0CLK/
COM4		 PM_UCA0CLK eUSCI_A0 clock input/output (direction controlled by eUSCI)
P1.7/PM_UCB0CLK/
COM5		 P1.7/PM_UCB0CLK/
COM5		 PM_UCB0CLK eUSCI_B0 clock input/output (direction controlled by eUSCI)
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6		 P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/S39		 PM_UCB0SOMI,
PM_UCB0SCL		 eUSCI_B0 SPI slave out master in
(direction controlled by eUSCI),
eUSCI_B0 I2C clock
(open drain and direction controlled by eUSCI)
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7		 P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/S38		 PM_UCB0SIMO,
PM_UCB0SDA		 eUSCI_B0 SPI slave in master out
(direction controlled by eUSCI),
eUSCI_B0 I2C data
(open drain and direction controlled by eUSCI)
P2.2/PM_UCA2RXD/
PM_UCA2SOMI		 P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37		 PM_UCA2RXD,
PM_UCA2SOMI		 eUSCI_A2 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A2 SPI slave out master in
(direction controlled by eUSCI)
P2.3/PM_UCA2TXD/
PM_UCA2SIMO		 P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36		 PM_UCA2TXD,
PM_UCA2SIMO		 eUSCI_A2 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A2 SPI slave in master out
(direction controlled by eUSCI)
P2.4/PM_UCA1CLK P2.4/PM_UCA1CLK/S35 PM_UCA1CLK eUSCI_A1 clock input/output (direction controlled by eUSCI)
P2.5/PM_UCA2CLK P2.5/PM_UCA2CLK/S34 PM_UCA2CLK eUSCI_A2 clock input/output (direction controlled by eUSCI)
P2.6/PM_TA1.0 P2.6/PM_TA1.0/S33 PM_TA1.0 TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0
P2.7/PM_TA1.1 P2.7/PM_TA1.1/S32 PM_TA1.1 TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
P3.0/PM_TA2.0 P3.0/PM_TA2.0/S31 PM_TA2.0 TA2 CCR0 capture input CCI0A TA2 CCR0 compare output Out0
P3.1/PM_TA2.1 P3.1/PM_TA2.1/S30 PM_TA2.1 TA2 CCR1 capture input CCI1A TA2 CCR1 compare output Out1
P3.2/PM_TACLK/
PM_RTCCLK		 P3.2/PM_TACLK/ PM_RTCCLK/S29 PM_TACLK,
PM_RTCCLK		 Timer_A clock input to
TA0, TA1, TA2, TA3		 RTC_C clock output
P3.3/PM_TA0.2 P3.3/PM_TA0.2/S28 PM_TA0.2 TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
P3.4/PM_SDCLK/S39 P3.4/PM_SDCLK/S27 PM_SDCLK SD24_B bitstream clock input/output
(direction controlled by SD24_B)
P3.5/PM_SD0DIO/S38 P3.5/PM_SD0DIO/S26 PM_SD0DIO SD24_B converter-0 bitstream data input/output
(direction controlled by SD24_B)
P3.6/PM_SD1DIO/S37 P3.6/PM_SD1DIO/S25 PM_SD1DIO SD24_B converter-1 bitstream data input/output
(direction controlled by SD24_B)
P3.7/PM_SD2DIO/S36 P3.7/PM_SD2DIO/S24 PM_SD2DIO SD24_B converter-2 bitstream data input/output
(direction controlled by SD24_B)