SLAS731D December   2011  – September 2018 MSP430F6720 , MSP430F6721 , MSP430F6723 , MSP430F6724 , MSP430F6725 , MSP430F6726 , MSP430F6730 , MSP430F6731 , MSP430F6733 , MSP430F6734 , MSP430F6735 , MSP430F6736

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-3 Terminal Functions, PZ Package
      2. Table 4-4 Terminal Functions, PN Package
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Thermal Resistance Characteristics
    8. 5.8  Digital I/O Ports
      1. Table 5-1 Schmitt-Trigger Inputs – General-Purpose I/O
      2. Table 5-2 Inputs – Ports P1 and P2
      3. Table 5-3 Leakage Current – General-Purpose I/O
      4. Table 5-4 Outputs – General-Purpose I/O (Full Drive Strength)
      5. Table 5-5 Typical Characteristics – General-Purpose I/O (Full Drive Strength)
      6. Table 5-6 Outputs – General-Purpose I/O (Reduced Drive Strength)
      7. 5.8.1     Typical Characteristics – General-Purpose I/O (Reduced Drive Strength)
      8. Table 5-7 Output Frequency – General-Purpose I/O
    9. 5.9  Clock Specifications
      1. Table 5-8  Crystal Oscillator, XT1, Low-Frequency Mode
      2. Table 5-9  Internal Very-Low-Power Low-Frequency Oscillator (VLO)
      3. Table 5-10 Internal Reference, Low-Frequency Oscillator (REFO)
      4. Table 5-11 DCO Frequency
    10. 5.10 Power-Management Module (PMM)
      1. Table 5-12 PMM, Brownout Reset (BOR)
      2. Table 5-13 PMM, Core Voltage
      3. Table 5-14 PMM, SVS High Side
      4. Table 5-15 PMM, SVM High Side
      5. Table 5-16 PMM, SVS Low Side
      6. Table 5-17 PMM, SVM Low Side
      7. Table 5-18 Wake-up Times From Low-Power Modes and Reset
    11. 5.11 Auxiliary Supplies
      1. Table 5-19 Auxiliary Supplies, Recommended Operating Conditions
      2. Table 5-20 Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents
      3. Table 5-21 Auxiliary Supplies, Auxiliary Supply Monitor
      4. Table 5-22 Auxiliary Supplies, Switch ON-Resistance
      5. Table 5-23 Auxiliary Supplies, Switching Time
      6. Table 5-24 Auxiliary Supplies, Switch Leakage
      7. Table 5-25 Auxiliary Supplies, Auxiliary Supplies to ADC10_A
      8. Table 5-26 Auxiliary Supplies, Charge Limiting Resistor
    12. 5.12 Timer_A
      1. Table 5-27 Timer_A
    13. 5.13 eUSCI
      1. Table 5-28 eUSCI (UART Mode) Clock Frequency
      2. Table 5-29 eUSCI (UART Mode) Switching Characteristics
      3. Table 5-30 eUSCI (SPI Master Mode) Clock Frequency
      4. Table 5-31 eUSCI (SPI Master Mode) Switching Characteristics
      5. Table 5-32 eUSCI (SPI Slave Mode)
      6. Table 5-33 eUSCI (I2C Mode)
    14. 5.14 LCD Controller
      1. Table 5-34 LCD_C Recommended Operating Conditions
      2. Table 5-35 LCD_C Electrical Characteristics
    15. 5.15 SD24_B
      1. Table 5-36 SD24_B Power Supply and Recommended Operating Conditions
      2. Table 5-37 SD24_B Analog Input
      3. Table 5-38 SD24_B Supply Currents
      4. Table 5-39 SD24_B Performance
      5. Table 5-40 SD24_B AC Performance
      6. Table 5-41 SD24_B AC Performance
      7. Table 5-42 SD24_B AC Performance
      8. Table 5-43 SD24_B External Reference Input
    16. 5.16 ADC10_A
      1. Table 5-44 10-Bit ADC, Power Supply and Input Range Conditions
      2. Table 5-45 10-Bit ADC, Timing Parameters
      3. Table 5-46 10-Bit ADC, Linearity Parameters
      4. Table 5-47 10-Bit ADC, External Reference
    17. 5.17 REF
      1. Table 5-48 REF, Built-In Reference
    18. 5.18 Flash Memory
      1. Table 5-49 Flash Memory
    19. 5.19 Emulation and Debug
      1. Table 5-50 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  Flash Memory
    9. 6.9  RAM
    10. 6.10 Backup RAM
    11. 6.11 Peripherals
      1. 6.11.1  Oscillator and System Clock
      2. 6.11.2  Power Management Module (PMM)
      3. 6.11.3  Auxiliary Supply System
      4. 6.11.4  Backup Subsystem
      5. 6.11.5  Digital I/O
      6. 6.11.6  Port Mapping Controller
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  Watchdog Timer (WDT_A)
      9. 6.11.9  DMA Controller
      10. 6.11.10 CRC16
      11. 6.11.11 Hardware Multiplier
      12. 6.11.12 Enhanced Universal Serial Communication Interface (eUSCI)
      13. 6.11.13 ADC10_A
      14. 6.11.14 SD24_B
      15. 6.11.15 TA0
      16. 6.11.16 TA1
      17. 6.11.17 TA2
      18. 6.11.18 TA3
      19. 6.11.19 SD24_B Triggers
      20. 6.11.20 ADC10_A Triggers
      21. 6.11.21 Real-Time Clock (RTC_C)
      22. 6.11.22 Reference (REF) Module Voltage Reference
      23. 6.11.23 LCD_C
      24. 6.11.24 Embedded Emulation Module (EEM) (S Version)
      25. 6.11.25 Peripheral File Map
    12. 6.12 Input/Output Diagrams
      1. 6.12.1  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN)
      2. 6.12.2  Port P1 (P1.2) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN)
      3. 6.12.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN)
      4. 6.12.4  Port P1 (P1.6 and P1.7) (MSP430F67xxIPZ and MSP430F67xxIPN), Port P2 (P2.0 and P2.1) (MSP430F67xxIPZ Only) Input/Output With Schmitt Trigger
      5. 6.12.5  Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      6. 6.12.6  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      7. 6.12.7  Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      8. 6.12.8  Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      9. 6.12.9  Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      10. 6.12.10 Port P9 (P9.0) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      11. 6.12.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      12. 6.12.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
      13. 6.12.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
      14. 6.12.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
      15. 6.12.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
      16. 6.12.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      17. 6.12.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    13. 6.13 Device Descriptors (TLV)
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.2 Signal Descriptions

Table 4-3 describes the signals for all device variants in the PZ package. See Table 4-4 for signal descriptions in the PN package.

Table 4-3 Terminal Functions, PZ Package

TERMINAL I/O(1) DESCRIPTION
NAME NO.
PZ
SD0P0 1 I SD24_B positive analog input for converter 0(3)
SD0N0 2 I SD24_B negative analog input for converter 0(3)
SD1P0 3 I SD24_B positive analog input for converter 1(3)
SD1N0 4 I SD24_B negative analog input for converter 1(3)
SD2P0 5 I SD24_B positive analog input for converter 2(3) (not available on F672x devices)
SD2N0 6 I SD24_B negative analog input for converter 2(3) (not available on F672x devices)
VREF 7 I SD24_B external reference voltage
AVSS 8 Analog ground supply
AVCC 9 Analog power supply
VASYS 10 Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS (see Table 5-19).
P9.1/A5 11 I/O

General-purpose digital I/O

Analog input A5 for 10-bit ADC
P9.2/A4 12 I/O

General-purpose digital I/O

Analog input A4 for 10-bit ADC
P9.3/A3 13 I/O

General-purpose digital I/O

Analog input A3 for 10-bit ADC
P1.0/PM_TA0.0/VeREF-/A2 14 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

Negative terminal for the ADC reference voltage for an external applied reference voltage

Analog input A2 for 10-bit ADC
P1.1/PM_TA0.1/VeREF+/A1 15 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output

Positive terminal for the ADC reference voltage for an external applied reference voltage

Analog input A1 for 10-bit ADC
P1.2/PM_UCA0RXD/ PM_UCA0SOMI/A0 16 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A0 UART receive data; eUSCI_A0 SPI slave out/master in

Analog input A0 for 10-bit ADC
P1.3/PM_UCA0TXD/ PM_UCA0SIMO/R03 17 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A0 UART transmit data; eUSCI_A0 SPI slave in/master out

Input/output port of lowest analog LCD voltage (V5)
AUXVCC2 18 Auxiliary power supply AUXVCC2
AUXVCC1 19 Auxiliary power supply AUXVCC1
VDSYS(4) 20 Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS (see Table 5-19).
DVCC 21 Digital power supply
DVSS 22 Digital ground supply
VCORE(2) 23 Regulated core power supply (internal use only, no external current loading)
XIN 24 I Input terminal for crystal oscillator
XOUT 25 O Output terminal for crystal oscillator
AUXVCC3 26 Auxiliary power supply AUXVCC3 for back up subsystem
P1.4/PM_UCA1RXD/ PM_UCA1SOMI/LCDREF/R13 27 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A1 UART receive data; eUSCI_A1 SPI slave out/master in

External reference voltage input for regulated LCD voltage

Input/output port of third most positive analog LCD voltage (V3 or V4)
P1.5/PM_UCA1TXD/ PM_UCA1SIMO/R23 28 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A1 UART transmit data; eUSCI_A1 SPI slave in/master out

Input/output port of second most positive analog LCD voltage (V2)
LCDCAP/R33 29 I/O

LCD capacitor connection

Input/output port of most positive analog LCD voltage (V1)

CAUTION: This pin must be connected to DVSS if not used.
P8.4/TA1.0 30 I/O

General-purpose digital I/O

Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output
P8.5/TA1.1 31 I/O

General-purpose digital I/O

Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output
COM0 32 O LCD common output COM0 for LCD backplane
COM1 33 O LCD common output COM1 for LCD backplane
COM2 34 O LCD common output COM2 for LCD backplane
COM3 35 O LCD common output COM3 for LCD backplane
P1.6/PM_UCA0CLK/COM4 36 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A0 clock input/output

LCD common output COM4 for LCD backplane
P1.7/PM_UCB0CLK/COM5 37 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 clock input/output

LCD common output COM5 for LCD backplane
P2.0/PM_UCB0SOMI/ PM_UCB0SCL/COM6 38 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock

LCD common output COM6 for LCD backplane
P2.1/PM_UCB0SIMO/ PM_UCB0SDA/COM7 39 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data

LCD common output COM7 for LCD backplane
P8.6/TA2.0 40 I/O

General-purpose digital I/O

Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output
P8.7/TA2.1 41 I/O

General-purpose digital I/O

Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output
P9.0/TACLK/RTCCLK 42 I/O

General-purpose digital I/O

Timer clock input TACLK for TA0, TA1, TA2, TA3

RTCCLK clock output
P2.2/PM_UCA2RXD/ PM_UCA2SOMI 43 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A2 UART receive data; eUSCI_A2 SPI slave out/master in
P2.3/PM_UCA2TXD/ PM_UCA2SIMO 44 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A2 UART transmit data; eUSCI_A2 SPI slave in/master out
P2.4/PM_UCA1CLK 45 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A1 clock input/output
P2.5/PM_UCA2CLK 46 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A2 clock input/output
P2.6/PM_TA1.0 47 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
P2.7/PM_TA1.1 48 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
P3.0/PM_TA2.0/BSL_TX 49 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output

Bootloader: Data transmit
P3.1/PM_TA2.1/BSL_RX 50 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1 output

Bootloader: Data receive
P3.2/PM_TACLK/PM_RTCCLK 51 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3; RTCCLK clock output
P3.3/PM_TA0.2 52 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
P3.4/PM_SDCLK/S39 53 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: SD24_B bitstream clock input/output

LCD segment output S39
P3.5/PM_SD0DIO/S38 54 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: SD24_B converter-0 bitstream data input/output

LCD segment output S38
P3.6/PM_SD1DIO/S37 55 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: SD24_B converter-1 bitstream data input/output

LCD segment output S37
P3.7/PM_SD2DIO/S36 56 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: SD24_B converter-2 bitstream data input/output (not available on F672x devices)

LCD segment output S36
P4.0/S35 57 I/O

General-purpose digital I/O

LCD segment output S35
P4.1/S34 58 I/O

General-purpose digital I/O

LCD segment output S34
P4.2/S33 59 I/O

General-purpose digital I/O

LCD segment output S33
P4.3/S32 60 I/O

General-purpose digital I/O

LCD segment output S32
P4.4/S31 61 I/O

General-purpose digital I/O

LCD segment output S31
P4.5/S30 62 I/O

General-purpose digital I/O

LCD segment output S30
P4.6/S29 63 I/O

General-purpose digital I/O

LCD segment output S29
P4.7/S28 64 I/O

General-purpose digital I/O

LCD segment output S28
P5.0/S27 65 I/O

General-purpose digital I/O

LCD segment output S27
P5.1/S26 66 I/O

General-purpose digital I/O

LCD segment output S26
P5.2/S25 67 I/O

General-purpose digital I/O

LCD segment output S25
P5.3/S24 68 I/O

General-purpose digital I/O

LCD segment output S24
P5.4/S23 69 I/O

General-purpose digital I/O

LCD segment output S23
P5.5/S22 70 I/O

General-purpose digital I/O

LCD segment output S22
P5.6/S21 71 I/O

General-purpose digital I/O

LCD segment output S21
P5.7/S20 72 I/O

General-purpose digital I/O

LCD segment output S20
P6.0/S19 73 I/O

General-purpose digital I/O

LCD segment output S19
DVSYS(4) 74 Digital power supply for I/Os
DVSS 75 Digital ground supply
P6.1/S18 76 I/O

General-purpose digital I/O

LCD segment output S18
P6.2/S17 77 I/O

General-purpose digital I/O

LCD segment output S17
P6.3/S16 78 I/O

General-purpose digital I/O

LCD segment output S16
P6.4/S15 79 I/O

General-purpose digital I/O

LCD segment output S15
P6.5/S14 80 I/O

General-purpose digital I/O

LCD segment output S14
P6.6/S13 81 I/O

General-purpose digital I/O

LCD segment output S13
P6.7/S12 82 I/O

General-purpose digital I/O

LCD segment output S12
P7.0/S11 83 I/O

General-purpose digital I/O

LCD segment output S11
P7.1/S10 84 I/O

General-purpose digital I/O

LCD segment output S10
P7.2/S9 85 I/O

General-purpose digital I/O

LCD segment output S9
P7.3/S8 86 I/O

General-purpose digital I/O

LCD segment output S8
P7.4/S7 87 I/O

General-purpose digital I/O

LCD segment output S7
P7.5/S6 88 I/O

General-purpose digital I/O

LCD segment output S6
P7.6/S5 89 I/O

General-purpose digital I/O

LCD segment output S5
P7.7/S4 90 I/O

General-purpose digital I/O

LCD segment output S4
P8.0/S3 91 I/O

General-purpose digital I/O

LCD segment output S3
P8.1/S2 92 I/O

General-purpose digital I/O

LCD segment output S2
P8.2/S1 93 I/O

General-purpose digital I/O

LCD segment output S1
P8.3/S0 94 I/O

General-purpose digital I/O

LCD segment output S0
TEST/SBWTCK 95 I

Test mode pin – select digital I/O on JTAG pins

Spy-Bi-Wire input clock
PJ.0/SMCLK/TDO 96 I/O

General-purpose digital I/O

SMCLK clock output

Test data output
PJ.1/MCLK/TDI/TCLK 97 I/O

General-purpose digital I/O

MCLK clock output

Test data input or Test clock input
PJ.2/ADC10CLK/TMS 98 I/O

General-purpose digital I/O

ADC10_A clock output

Test mode select
PJ.3/ACLK/TCK 99 I/O

General-purpose digital I/O

ACLK clock output

Test clock
RST/NMI/SBWTDIO 100 I/O

Reset input active low(5)

Nonmaskable interrupt input

Spy-Bi-Wire data input/output
(1) I = input, O = output
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE.
(3) Short unused analog input pairs and connect them to analog ground.
(4) The pins VDSYS and DVSYS must be connected externally on the board for proper device operation.
(5) When this pin is configured as reset, the internal pullup resistor is enabled by default.

Table 4-4 describes the signals for all device variants in the PN package. See Table 4-3 for signal descriptions in the PZ package.

Table 4-4 Terminal Functions, PN Package

TERMINAL I/O(1) DESCRIPTION
NAME NO.
PN
SD0P0 1 I SD24_B positive analog input for converter 0(3)
SD0N0 2 I SD24_B negative analog input for converter 0(3)
SD1P0 3 I SD24_B positive analog input for converter 1(3)
SD1N0 4 I SD24_B negative analog input for converter 1(3)
SD2P0 5 I SD24_B positive analog input for converter 2(3) (not available on F672x devices)
SD2N0 6 I SD24_B negative analog input for converter 2(3) (not available on F672x devices)
VREF 7 I SD24_B external reference voltage
AVSS 8 Analog ground supply
AVCC 9 Analog power supply
VASYS 10 Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS (see Table 5-19).
P1.0/PM_TA0.0/VeREF-/A2 11 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

Negative terminal for the ADC reference voltage for an external applied reference voltage

Analog input A2 for 10-bit ADC
P1.1/PM_TA0.1/VeREF+/A1 12 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output

Positive terminal for the ADC reference voltage for an external applied reference voltage

Analog input A1 for 10-bit ADC
P1.2/PM_UCA0RXD/ PM_UCA0SOMI/A0 13 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A0 UART receive data; eUSCI_A0 SPI slave out/master in

Analog input A0 for 10-bit ADC
P1.3/PM_UCA0TXD/ PM_UCA0SIMO/R03 14 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A0 UART transmit data; eUSCI_A0 SPI slave in/master out

Input/output port of lowest analog LCD voltage (V5)
AUXVCC2 15 Auxiliary power supply AUXVCC2
AUXVCC1 16 Auxiliary power supply AUXVCC1
VDSYS(4) 17 Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS (see Table 5-19).
DVCC 18 Digital power supply
DVSS 19 Digital ground supply
VCORE(2) 20 Regulated core power supply (internal use only, no external current loading)
XIN 21 I Input terminal for crystal oscillator
XOUT 22 O Output terminal for crystal oscillator
AUXVCC3 23 Auxiliary power supply AUXVCC3 for back up subsystem
P1.4/PM_UCA1RXD/ PM_UCA1SOMI/LCDREF/R13 24 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A1 UART receive data; eUSCI_A1 SPI slave out/master in

External reference voltage input for regulated LCD voltage

Input/output port of third most positive analog LCD voltage (V3 or V4)
P1.5/PM_UCA1TXD/ PM_UCA1SIMO/R23 25 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A1 UART transmit data; eUSCI_A1 SPI slave in/master out

Input/output port of second most positive analog LCD voltage (V2)
LCDCAP/R33 26 I/O

LCD capacitor connection

Input/output port of most positive analog LCD voltage (V1)

CAUTION: This pin must be connected to DVSS if not used.
COM0 27 O LCD common output COM0 for LCD backplane
COM1 28 O LCD common output COM1 for LCD backplane
COM2 29 O LCD common output COM2 for LCD backplane
COM3 30 O LCD common output COM3 for LCD backplane
P1.6/PM_UCA0CLK/COM4 31 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A0 clock input/output

LCD common output COM4 for LCD backplane
P1.7/PM_UCB0CLK/COM5 32 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 clock input/output

LCD common output COM5 for LCD backplane
P2.0/PM_UCB0SOMI/ PM_UCB0SCL/COM6/S39 33 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock

LCD common output COM6 for LCD backplane

LCD segment output S39
P2.1/PM_UCB0SIMO/ PM_UCB0SDA/COM7/S38 34 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data

LCD common output COM7 for LCD backplane

LCD segment output S38
P2.2/PM_UCA2RXD/ PM_UCA2SOMI/S37 35 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A2 UART receive data; eUSCI_A2 SPI slave out/master in

LCD segment output S37
P2.3/PM_UCA2TXD/ PM_UCA2SIMO/S36 36 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A2 UART transmit data; eUSCI_A2 SPI slave in/master out

LCD segment output S36
P2.4/PM_UCA1CLK/S35 37 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A1 clock input/output

LCD segment output S35
P2.5/PM_UCA2CLK/S34 38 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A2 clock input/output

LCD segment output S34
P2.6/PM_TA1.0/S33 39 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output

LCD segment output S33
P2.7/PM_TA1.1/S32 40 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1 output

LCD segment output S32
P3.0/PM_TA2.0/S31/BSL_TX 41 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output

LCD segment output S31

Bootloader: Data transmit
P3.1/PM_TA2.1/S30/BSL_RX 42 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1 output

LCD segment output S30

Bootloader: Data receive
P3.2/PM_TACLK/PM_RTCCLK/ S29 43 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3; RTCCLK clock output

LCD segment output S29
P3.3/PM_TA0.2/S28 44 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output

LCD segment output S28
P3.4/PM_SDCLK/S27 45 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: SD24_B bitstream clock input/output

LCD segment output S27
P3.5/PM_SD0DIO/S26 46 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: SD24_B converter-0 bitstream data input/output

LCD segment output S26
P3.6/PM_SD1DIO/S25 47 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: SD24_B converter-1 bitstream data input/output

LCD segment output S25
P3.7/PM_SD2DIO/S24 48 I/O

General-purpose digital I/O with mappable secondary function

Default mapping: SD24_B converter-2 bitstream data input/output (not available on F672x devices)

LCD segment output S24
P4.0/S23 49 I/O

General-purpose digital I/O

LCD segment output S23
P4.1/S22 50 I/O

General-purpose digital I/O

LCD segment output S22
P4.2/S21 51 I/O

General-purpose digital I/O

LCD segment output S21
P4.3/S20 52 I/O

General-purpose digital I/O

LCD segment output S20
P4.4/S19 53 I/O

General-purpose digital I/O

LCD segment output S19
P4.5/S18 54 I/O

General-purpose digital I/O

LCD segment output S18
P4.6/S17 55 I/O

General-purpose digital I/O

LCD segment output S17
P4.7/S16 56 I/O

General-purpose digital I/O

LCD segment output S16
P5.0/S15 57 I/O

General-purpose digital I/O

LCD segment output S15
P5.1/S14 58 I/O

General-purpose digital I/O

LCD segment output S14
DVSYS(4) 59 Digital power supply for I/Os
DVSS 60 Digital ground supply
P5.2/S13 61 I/O

General-purpose digital I/O

LCD segment output S13
P5.3/S12 62 I/O

General-purpose digital I/O

LCD segment output S12
P5.4/S11 63 I/O

General-purpose digital I/O

LCD segment output S11
P5.5/S10 64 I/O

General-purpose digital I/O

LCD segment output S10
P5.6/S9 65 I/O

General-purpose digital I/O

LCD segment output S9
P5.7/S8 66 I/O

General-purpose digital I/O

LCD segment output S8
P6.0/S7 67 I/O

General-purpose digital I/O

LCD segment output S7
P6.1/S6 68 I/O

General-purpose digital I/O

LCD segment output S6
P6.2/S5 69 I/O

General-purpose digital I/O

LCD segment output S5
P6.3/S4 70 I/O

General-purpose digital I/O

LCD segment output S4
P6.4/S3 71 I/O

General-purpose digital I/O

LCD segment output S3
P6.5/S2 72 I/O

General-purpose digital I/O

LCD segment output S2
P6.6/S1 73 I/O

General-purpose digital I/O

LCD segment output S1
P6.7/S0 74 I/O

General-purpose digital I/O

LCD segment output S0
TEST/SBWTCK 75 I

Test mode pin – select digital I/O on JTAG pins

Spy-Bi-Wire input clock
PJ.0/SMCLK/TDO 76 I/O

General-purpose digital I/O

SMCLK clock output

Test data output
PJ.1/MCLK/TDI/TCLK 77 I/O

General-purpose digital I/O

MCLK clock output

Test data input or Test clock input
PJ.2/ADC10CLK/TMS 78 I/O

General-purpose digital I/O

ADC10_A clock output

Test mode select
PJ.3/ACLK/TCK 79 I/O

General-purpose digital I/O

ACLK clock output

Test clock
RST/NMI/SBWTDIO 80 I/O

Reset input active low(5)

Nonmaskable interrupt input

Spy-Bi-Wire data input/output
(1) I = input, O = output
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE.
(3) Short unused analog input pairs and connect them to analog ground.
(4) The pins VDSYS and DVSYS must be connected externally on the board for proper device operation.
(5) When this pin is configured as reset, the internal pullup resistor is enabled by default.