SLAS731D December 2011 – September 2018 MSP430F6720 , MSP430F6721 , MSP430F6723 , MSP430F6724 , MSP430F6725 , MSP430F6726 , MSP430F6730 , MSP430F6731 , MSP430F6733 , MSP430F6734 , MSP430F6735 , MSP430F6736
PRODUCTION DATA.
Figure 6-18 shows the port diagram. Table 6-80 summarizes the selection of the pin functions.
PIN NAME (PJ.x) | x | FUNCTION | CONTROL BITS OR SIGNALS(2) | |||
---|---|---|---|---|---|---|
PJDIR.x | PJSEL.x | JTAG Mode Signal | ||||
PJ.0/SMCLK/TDO | 0 | PJ.0 (I/O)(1) | I: 0; O: 1 | 0 | 0 | |
SMCLK | 1 | 1 | 0 | |||
TDO(2) | X | X | 1 | |||
PJ.1/MCLK/TDI/TCLK | 1 | PJ.1 (I/O)(1) | I: 0; O: 1 | 0 | 0 | |
MCLK | 1 | 1 | 0 | |||
TDI/TCLK (2)(3) | X | X | 1 | |||
PJ.2/ADC10CLK/TMS | 2 | PJ.2 (I/O)(1) | I: 0; O: 1 | 0 | 0 | |
ADC10CLK | 1 | 1 | 0 | |||
TMS (2)(3) | X | X | 1 | |||
PJ.3/ACLK/TCK | 3 | PJ.3 (I/O)(1) | I: 0; O: 1 | 0 | 0 | |
ACLK | 1 | 1 | 0 | |||
TCK (2)(3) | X | X | 1 |