SLAS815 Data sheet

SLAS815D November 2012 – September 2018 MSP430F67451 , MSP430F67461 , MSP430F67471 , MSP430F67481 , MSP430F67491 , MSP430F67651 , MSP430F67661 , MSP430F67671 , MSP430F67681 , MSP430F67691 , MSP430F67751 , MSP430F67761 , MSP430F67771 , MSP430F67781 , MSP430F67791

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

PZ|100
- MTQF013A

Thermal pad, mechanical data (Package|Pins)

PZ|100
- QFND428

Orderable Information

5.40 eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE low to clock		2 V	4		ns
t_STE,LEAD	STE lead time, STE low to clock		3 V	3		ns
t_STE,LAG	STE lag time, Last clock to STE high		2 V	0		ns
t_STE,LAG	STE lag time, Last clock to STE high		3 V	0		ns
t_STE,ACC	STE access time, STE low to SOMI data out		2 V		46	ns
t_STE,ACC	STE access time, STE low to SOMI data out		3 V		24	ns
t_STE,DIS	STE disable time, STE high to SOMI high impedance		2 V		38	ns
t_STE,DIS	STE disable time, STE high to SOMI high impedance		3 V		25	ns
t_SU,SI	SIMO input data setup time		2 V	2		ns
t_SU,SI	SIMO input data setup time		3 V	1		ns
t_HD,SI	SIMO input data hold time		2 V	2		ns
t_HD,SI	SIMO input data hold time		3 V	2		ns
t_VALID,SO	SOMI output data valid time⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	2 V		55	ns
t_VALID,SO	SOMI output data valid time⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	3 V		32	ns
t_HD,SO	SOMI output data hold time⁽³⁾	C_L = 20 pF	2 V	24		ns
t_HD,SO	SOMI output data hold time⁽³⁾	C_L = 20 pF	3 V	16		ns

(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)})
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14.

MSP430F67791 MSP430F67781 MSP430F67771 MSP430F67761 MSP430F67751 MSP430F67691 MSP430F67681 MSP430F67671 MSP430F67661 MSP430F67651 MSP430F67491 MSP430F67481 MSP430F67471 MSP430F67461 MSP430F67451 slas639-eUSCI_slave_CKPH0.gif

Figure 5-13 SPI Slave Mode, CKPH = 0

Figure 5-14 SPI Slave Mode, CKPH = 1