SLAS982A May   2014  – September 2018 MSP430F6745A , MSP430F6746A , MSP430F6747A , MSP430F6748A , MSP430F6749A , MSP430F6765A , MSP430F6766A , MSP430F6767A , MSP430F6768A , MSP430F6769A , MSP430F6775A , MSP430F6776A , MSP430F6777A , MSP430F6778A , MSP430F6779A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Application Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-3 Terminal Functions – PEU Package
      2. Table 4-4 Terminal Functions – PZ Package
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Thermal Resistance Characteristics
    8. 5.8  Timing and Switching Characteristics
      1. 5.8.1 Reset Timing
        1. Table 5-1 Wake-up Times From Low-Power Modes and Reset
      2. 5.8.2 Clock Specifications
        1. Table 5-2 Crystal Oscillator, XT1, Low-Frequency Mode
        2. Table 5-3 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        3. Table 5-4 Internal Reference, Low-Frequency Oscillator (REFO)
        4. Table 5-5 DCO Frequency
    9. 5.9  Digital I/Os
      1. Table 5-6  Schmitt-Trigger Inputs – General-Purpose I/O
      2. Table 5-7  Inputs – Ports P1 and P2
      3. Table 5-8  Leakage Current – General-Purpose I/O
      4. Table 5-9  Outputs – General-Purpose I/O (Full Drive Strength)
      5. Table 5-10 Outputs – General-Purpose I/O (Reduced Drive Strength)
      6. Table 5-11 Output Frequency – General-Purpose I/O
      7. 5.9.1      Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
      8. 5.9.2      Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    10. 5.10 Power-Management Module (PMM)
      1. Table 5-12 PMM, Brownout Reset (BOR)
      2. Table 5-13 PMM, Core Voltage
      3. Table 5-14 PMM, SVS High Side
      4. Table 5-15 PMM, SVM High Side
      5. Table 5-16 PMM, SVS Low Side
      6. Table 5-17 PMM, SVM Low Side
    11. 5.11 Auxiliary Supplies
      1. Table 5-18 Auxiliary Supplies, Recommended Operating Conditions
      2. Table 5-19 Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents
      3. Table 5-20 Auxiliary Supplies, Auxiliary Supply Monitor
      4. Table 5-21 Auxiliary Supplies, Switch ON-Resistance
      5. Table 5-22 Auxiliary Supplies, Switching Time
      6. Table 5-23 Auxiliary Supplies, Switch Leakage
      7. Table 5-24 Auxiliary Supplies, Auxiliary Supplies to ADC10_A
      8. Table 5-25 Auxiliary Supplies, Charge Limiting Resistor
    12. 5.12 Timer_A
      1. Table 5-26 Timer_A
    13. 5.13 eUSCI
      1. Table 5-27 eUSCI (UART Mode) Clock Frequency
      2. Table 5-28 eUSCI (UART Mode) Switching Characteristics
      3. Table 5-29 eUSCI (SPI Master Mode) Clock Frequency
      4. Table 5-30 eUSCI (SPI Master Mode) Switching Characteristics
      5. Table 5-31 eUSCI (SPI Slave Mode)
      6. Table 5-32 eUSCI (I2C Mode) Switching Characteristics
    14. 5.14 RTC Tamper Detect Pin
      1. Table 5-33 Schmitt-Trigger Inputs, RTC Tamper Detect Pin
      2. Table 5-34 Inputs, RTC Tamper Detect Pin
      3. Table 5-35 Leakage Current, RTC Tamper Detect Pin
      4. Table 5-36 Outputs, RTC Tamper Detect Pin
    15. 5.15 LCD_C
      1. Table 5-37 LCD_C, Operating Conditions
      2. Table 5-38 LCD_C, Electrical Characteristics
    16. 5.16 SD24_B
      1. Table 5-39 SD24_B, Power Supply and Operating Conditions
      2. Table 5-40 SD24_B, Analog Inputs
      3. Table 5-41 SD24_B, Supply Currents
      4. Table 5-42 SD24_B, Performance
      5. Table 5-43 SD24_B, AC Performance
      6. Table 5-44 SD24_B, AC Performance
      7. Table 5-45 SD24_B, AC Performance
      8. Table 5-46 SD24_B External Reference Input
    17. 5.17 ADC10_A
      1. Table 5-47 10-Bit ADC, Power Supply and Input Range Conditions
      2. Table 5-48 10-Bit ADC, Switching Characteristics
      3. Table 5-49 10-Bit ADC, Linearity Parameters
      4. Table 5-50 10-Bit ADC, External Reference
    18. 5.18 REF
      1. Table 5-51 REF Built-In Reference
    19. 5.19 Comparator_B
      1. Table 5-52 Comparator_B
    20. 5.20 Flash
      1. Table 5-53 Flash Memory
    21. 5.21 Emulation and Debug
      1. Table 5-54 JTAG and Spy-Bi-Wire (SBW) Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagrams
    3. 6.3  CPU (Link to User's Guide)
    4. 6.4  Instruction Set
    5. 6.5  Operating Modes
    6. 6.6  Interrupt Vector Addresses
    7. 6.7  Special Function Registers (SFRs)
      1. Table 6-4 Interrupt Enable 1 Register Description
      2. Table 6-5 Interrupt Flag 1 Register Description
    8. 6.8  Bootloader (BSL)
    9. 6.9  JTAG Operation
      1. 6.9.1 JTAG Standard Interface
      2. 6.9.2 Spy-Bi-Wire Interface
    10. 6.10 Memory
      1. 6.10.1 Memory Organization
      2. 6.10.2 Flash Memory (Link to User's Guide)
      3. 6.10.3 RAM (Link to User's Guide)
      4. 6.10.4 Backup RAM (Link to User's Guide)
    11. 6.11 Peripherals
      1. 6.11.1  Oscillator and System Clock (Link to User's Guide)
      2. 6.11.2  Power-Management Module (PMM) (Link to User's Guide)
      3. 6.11.3  Auxiliary-Supply System (Link to User's Guide)
      4. 6.11.4  Backup Subsystem
      5. 6.11.5  Digital I/O (Link to User's Guide)
      6. 6.11.6  Port Mapping Controller (Link to User's Guide)
      7. 6.11.7  System Module (SYS) (Link to User's Guide)
      8. 6.11.8  Watchdog Timer (WDT_A) (Link to User's Guide)
      9. 6.11.9  DMA Controller (Link to User's Guide)
      10. 6.11.10 CRC16 (Link to User's Guide)
      11. 6.11.11 Hardware Multiplier (Link to User's Guide)
      12. 6.11.12 AES128 Accelerator (Link to User's Guide)
      13. 6.11.13 Enhanced Universal Serial Communication Interface (eUSCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      14. 6.11.14 ADC10_A (Link to User's Guide)
      15. 6.11.15 SD24_B (Link to User's Guide)
      16. 6.11.16 TA0 (Link to User's Guide)
      17. 6.11.17 TA1 (Link to User's Guide)
      18. 6.11.18 TA2 (Link to User's Guide)
      19. 6.11.19 TA3 (Link to User's Guide)
      20. 6.11.20 SD24_B Triggers
      21. 6.11.21 ADC10_A Triggers
      22. 6.11.22 Real-Time Clock (RTC_C) (Link to User's Guide)
      23. 6.11.23 Reference (REF) Module Voltage Reference (Link to User's Guide)
      24. 6.11.24 LCD_C (Link to User's Guide)
      25. 6.11.25 Comparator_B (Link to User's Guide)
      26. 6.11.26 Embedded Emulation Module (EEM) (Link to User's Guide)
      27. 6.11.27 Peripheral File Map
    12. 6.12 Input/Output Diagrams
      1. 6.12.1  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger (PEU Package Only)
      2. 6.12.2  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger (PZ Package Only)
      3. 6.12.3  Port P1 (P1.4 and P1.5) Input/Output With Schmitt Trigger
      4. 6.12.4  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      5. 6.12.5  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger (PEU Package Only)
      6. 6.12.6  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger (PZ Package Only)
      7. 6.12.7  Port P2 (P2.4 to P2.6) Input/Output With Schmitt Trigger (PZ Package Only)
      8. 6.12.8  Port P2 (P2.7) Input/Output With Schmitt Trigger (PZ Package Only)
      9. 6.12.9  Ports P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (PEU Package Only)
      10. 6.12.10 Ports P3 (P3.0) Input/Output With Schmitt Trigger (PZ Package Only)
      11. 6.12.11 Ports P3 (P3.1 to P3.7) Input/Output With Schmitt Trigger (PZ Package Only)
      12. 6.12.12 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (PEU Package Only)
      13. 6.12.13 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (PZ Package Only)
      14. 6.12.14 Port P5 (P5.0 to P5.3) Input/Output With Schmitt Trigger (PEU Package Only)
      15. 6.12.15 Port P5 (P5.4 to P5.6) Input/Output With Schmitt Trigger (PEU Package Only)
      16. 6.12.16 Port P5 (P5.7) Input/Output With Schmitt Trigger (PEU Package Only)
      17. 6.12.17 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger (PZ Package Only)
      18. 6.12.18 Port P6 (P6.0) Input/Output With Schmitt Trigger (PEU Package Only)
      19. 6.12.19 Port P6 (P6.1 to P6.3) Input/Output With Schmitt Trigger (PEU Package Only)
      20. 6.12.20 Port P6 (P6.4 to P6.7) Input/Output With Schmitt Trigger (PEU Package Only)
      21. 6.12.21 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (PZ Package Only)
      22. 6.12.22 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger (PEU Package Only)
      23. 6.12.23 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger (PZ Package Only)
      24. 6.12.24 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger (PEU Package Only)
      25. 6.12.25 Port P8 (P8.0) Input/Output With Schmitt Trigger (PZ Package Only)
      26. 6.12.26 Port P8 (P8.1) Input/Output With Schmitt Trigger (PZ Package Only)
      27. 6.12.27 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger (PEU Package Only)
      28. 6.12.28 Port P10 (P10.0 to P10.7) Input/Output With Schmitt Trigger (PEU Package Only)
      29. 6.12.29 Port P11 (P11.0) Input/Output With Schmitt Trigger (PEU Package Only)
      30. 6.12.30 Port P11 (P11.1) Input/Output With Schmitt Trigger (PEU Package Only)
      31. 6.12.31 Port P11 (P11.2 and P11.3) Input/Output With Schmitt Trigger (PEU Package Only)
      32. 6.12.32 Port P11 (P11.4 and P11.5) Input/Output With Schmitt Trigger (PEU Package Only)
      33. 6.12.33 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      34. 6.12.34 Port PJ (PJ.0 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    13. 6.13 Device Descriptors (TLV)
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.1 Pin Diagrams

Figure 4-1 shows the pinout for the 128-pin PEU package. Table 4-1 summarizes the differences in the pinout among the device variants.

MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A pinout_128_slas768.gif
A. The secondary digital functions on Ports P2, P3, and P4 are fully mappable. This pinout shows only the default mapping. See Section 6.11.6 for details.
B. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper device operation.
C. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.
Figure 4-1 128-Pin PEU Package (Top View)

Table 4-1 Pinout Differences for PEU Package, F677xA, F676xA, and F674xA

PIN NUMBER PIN NAME
MSP430F677xAIPEU MSP430F676xAIPEU MSP430F674xAIPEU
46 P6.1/SD4DIO/S39 P6.1/SD4DIO/S39 P6.1/S39
47 P6.2/SD5DIO/S38 P6.2/SD5DIO/S38 P6.2/S38
48 P6.3/SD6DIO/S37 P6.3/S37 P6.3/S37
113 VREF VREF VREF
114 SD4P0 SD4P0 NC
115 SD4N0 SD4N0 NC
116 SD5P0 SD5P0 NC
117 SD5N0 SD5NO NC
118 SD6P0 NC NC
119 SD6N0 NC NC

Figure 4-2 shows the pinout for the 100-pin PZ package. Table 4-2 summarizes the differences in the pinout among the device variants.

MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A pinout_100_slas768.gif
A. The secondary digital functions on Ports P2, P3, and P4 are fully mappable. This pinout shows only the default mapping. See Section 6.11.6 for details.
B. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper device operation.
C. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.
Figure 4-2 100-Pin PZ Package (Top View)

Table 4-2 Pinout Differences for PZ Package, F677xA, F676xA, and F674xA

PIN NUMBER PIN NAME
MSP430F677xAIPZ MSP430F676xAIPZ MSP430F674xAIPZ
11 VREF VREF VREF
12 SD4P0 SD4P0 NC
13 SD4N0 SD4N0 NC
14 SD5P0 SD5P0 NC
15 SD5N0 SD5NO NC
16 SD6P0 NC NC
17 SD6N0 NC NC
72 P5.5/SD4DIO/S19 P5.5/SD4DIO/S19 P5.5/S19
73 P5.6/SD5DIO/S18 P5.6/SD5DIO/S18 P5.6/S18
74 P5.7/SD6DIO/S17 P5.7/S17 P5.7/S17