SLASE50A
February 2015 – October 2018
MSP430F67621A
,
MSP430F67641A
PRODUCTION DATA.
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Application Diagram
2
Revision History
3
Device Comparison
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Pin Diagrams
4.2
Pin Attributes
4.3
Signal Descriptions
Table 4-3
Signal Descriptions – PZ Package
Table 4-4
Signal Descriptions – PN Package
4.4
Pin Multiplexing
4.5
Buffer Type
4.6
Connection of Unused Pins
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Active Mode Supply Current Into VCC Excluding External Current
5.5
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
5.6
Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
5.7
Thermal Resistance Characteristics
5.8
Timing and Switching Characteristics
5.8.1
Power Supply Sequencing
5.8.2
Reset Timing
Table 5-1
Wake-up Times From Low-Power Modes and Reset
5.8.3
Clock Specifications
Table 5-2
Crystal Oscillator, XT1, Low-Frequency Mode
Table 5-3
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
Table 5-4
Internal Reference, Low-Frequency Oscillator (REFO)
Table 5-5
DCO Frequency
5.8.4
Digital I/O Ports
Table 5-6
Schmitt-Trigger Inputs, General-Purpose I/O
Table 5-7
Inputs, Ports P1 and P2
Table 5-8
Leakage Current, General-Purpose I/O
Table 5-9
Outputs, General-Purpose I/O (Full Drive Strength)
5.8.4.1
Typical Characteristics, General-Purpose I/O (Full Drive Strength)
Table 5-10
Outputs, General-Purpose I/O (Reduced Drive Strength)
5.8.4.2
Typical Characteristics, General-Purpose I/O (Reduced Drive Strength)
Table 5-11
Output Frequency, General-Purpose I/O
5.8.5
Power-Management Module (PMM)
Table 5-12
PMM, Brownout Reset (BOR)
Table 5-13
PMM, Core Voltage
Table 5-14
PMM, SVS High Side
Table 5-15
PMM, SVM High Side
Table 5-16
PMM, SVS Low Side
Table 5-17
PMM, SVM Low Side
5.8.6
Auxiliary Supplies Module
Table 5-18
Auxiliary Supplies, Recommended Operating Conditions
Table 5-19
Auxiliary Supplies, AUX3 (Backup Subsystem) Currents
Table 5-20
Auxiliary Supplies, Auxiliary Supply Monitor
Table 5-21
Auxiliary Supplies, Switch ON-Resistance
Table 5-22
Auxiliary Supplies, Switching Time
Table 5-23
Auxiliary Supplies, Switch Leakage
Table 5-24
Auxiliary Supplies, Auxiliary Supplies to ADC10_A
Table 5-25
Auxiliary Supplies, Charge-Limiting Resistor
5.8.7
Timer_A Module
Table 5-26
Timer_A
5.8.8
eUSCI Module
Table 5-27
eUSCI (UART Mode) Clock Frequency
Table 5-28
eUSCI (UART Mode) Switching Characteristics
Table 5-29
eUSCI (SPI Master Mode) Clock Frequency
Table 5-30
eUSCI (SPI Master Mode) Switching Characteristics
Table 5-31
eUSCI (SPI Slave Mode)
Table 5-32
eUSCI (I2C Mode)
5.8.9
LCD Controller
Table 5-33
LCD_C Operating Conditions
Table 5-34
LCD_C Electrical Characteristics
5.8.10
SD24_B Module
Table 5-35
SD24_B Power Supply and Recommended Operating Conditions
Table 5-36
SD24_B Analog Input
Table 5-37
SD24_B Supply Currents
Table 5-38
SD24_B Performance
Table 5-39
SD24_B AC Performance
Table 5-40
SD24_B AC Performance
Table 5-41
SD24_B AC Performance
Table 5-42
SD24_B External Reference Input
5.8.11
ADC10_A Module
Table 5-43
10-Bit ADC, Power Supply and Input Range Conditions
Table 5-44
10-Bit ADC, Timing Parameters
Table 5-45
10-Bit ADC, Linearity Parameters
Table 5-46
10-Bit ADC, External Reference
5.8.12
REF Module
Table 5-47
REF, Built-In Reference
5.8.13
Flash
Table 5-48
Flash Memory
5.8.14
Emulation and Debug
Table 5-49
JTAG and Spy-Bi-Wire Interface
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagrams
6.3
CPU
6.4
Instruction Set
6.5
Operating Modes
6.6
Interrupt Vector Addresses
6.7
Bootloader (BSL)
6.8
JTAG Operation
6.8.1
JTAG Standard Interface
6.8.2
Spy-Bi-Wire Interface
6.9
Flash Memory
6.10
RAM
6.11
Backup RAM
6.12
Peripherals
6.12.1
Oscillator and System Clock
6.12.2
Power-Management Module (PMM)
6.12.3
Auxiliary Supply System
6.12.4
Backup Subsystem
6.12.5
Digital I/O
6.12.6
Port Mapping Controller
6.12.7
System Module (SYS)
6.12.8
Watchdog Timer (WDT_A)
6.12.9
DMA Controller
6.12.10
CRC16
6.12.11
Hardware Multiplier
6.12.12
Enhanced Universal Serial Communication Interface (eUSCI)
6.12.13
ADC10_A
6.12.14
SD24_B
6.12.15
TA0
6.12.16
TA1
6.12.17
TA2
6.12.18
TA3
6.12.19
SD24_B Triggers
6.12.20
ADC10_A Triggers
6.12.21
Real-Time Clock (RTC_C)
6.12.22
Reference (REF) Module Voltage Reference
6.12.23
LCD_C
6.12.24
Embedded Emulation Module (EEM) (S Version)
6.13
Input/Output Diagrams
6.13.1
Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
6.13.2
Port P1 (P1.2) Input/Output With Schmitt Trigger
6.13.3
Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
6.13.4
Port P1 (P1.6 and P1.7), Port P2 (P2.0 and P2.1) (PZ Package Only) Input/Output With Schmitt Trigger
6.13.5
Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (PZ Package Only)
6.13.6
Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (PZ Package Only)
6.13.7
Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (PZ Package Only)
6.13.8
Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (PZ Package Only)
6.13.9
Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (PZ Package Only)
6.13.10
Port P9 (P9.0), Input/Output With Schmitt Trigger (PZ Package Only)
6.13.11
Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (PZ Package Only)
6.13.12
Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (PN Package Only)
6.13.13
Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (PN Package Only)
6.13.14
Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (PN Package Only)
6.13.15
Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (PN Package Only)
6.13.16
Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
6.13.17
Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
6.14
Device Descriptors (TLV)
6.15
Memory
6.15.1
Peripheral File Map
6.16
Identification
6.16.1
Revision Identification
6.16.2
Device Identification
6.16.3
JTAG Identification
7
Applications, Implementation, and Layout
8
Device and Documentation Support
8.1
Getting Started and Next Steps
8.2
Device Nomenclature
8.3
Tools and Software
8.4
Documentation Support
8.5
Related Links
8.6
Community Resources
8.7
Trademarks
8.8
Electrostatic Discharge Caution
8.9
Export Control Notice
8.10
Glossary
9
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PN|80
MTQF010B
PZ|100
MTQF013A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slase50a_oa
slase50a_pm
5.8
Timing and Switching Characteristics