SLAS998A June   2014  – October 2018 MSP430F67621 , MSP430F67641

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Application Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions – PZ Package
      2. Table 4-2 Signal Descriptions – PN Package
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7 Thermal Resistance Characteristics
    8. 5.8 Timing and Switching Characteristics
      1. 5.8.1  Clock Specifications
        1. Table 5-1 Crystal Oscillator, XT1, Low-Frequency Mode
        2. Table 5-2 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        3. Table 5-3 Internal Reference, Low-Frequency Oscillator (REFO)
        4. Table 5-4 DCO Frequency
      2. 5.8.2  Digital I/O Ports
        1. Table 5-5  Schmitt-Trigger Inputs – General-Purpose I/O
        2. Table 5-6  Inputs – Ports P1 and P2
        3. Table 5-7  Leakage Current – General-Purpose I/O
        4. Table 5-8  Outputs – General-Purpose I/O (Full Drive Strength)
        5. Table 5-9  Typical Characteristics – General-Purpose I/O (Full Drive Strength)
        6. Table 5-10 Outputs – General-Purpose I/O (Reduced Drive Strength)
        7. 5.8.2.1    Typical Characteristics – General-Purpose I/O (Reduced Drive Strength)
        8. Table 5-11 Output Frequency – General-Purpose I/O
      3. 5.8.3  Power-Management Module (PMM)
        1. Table 5-12 PMM, Brownout Reset (BOR)
        2. Table 5-13 PMM, Core Voltage
        3. Table 5-14 PMM, SVS High Side
        4. Table 5-15 PMM, SVM High Side
        5. Table 5-16 PMM, SVS Low Side
        6. Table 5-17 PMM, SVM Low Side
        7. Table 5-18 Wake-up Times From Low-Power Modes and Reset
      4. 5.8.4  Auxiliary Supplies
        1. Table 5-19 Auxiliary Supplies, Recommended Operating Conditions
        2. Table 5-20 Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents
        3. Table 5-21 Auxiliary Supplies, Auxiliary Supply Monitor
        4. Table 5-22 Auxiliary Supplies, Switch ON-Resistance
        5. Table 5-23 Auxiliary Supplies, Switching Time
        6. Table 5-24 Auxiliary Supplies, Switch Leakage
        7. Table 5-25 Auxiliary Supplies, Auxiliary Supplies to ADC10_A
        8. Table 5-26 Auxiliary Supplies, Charge Limiting Resistor
      5. 5.8.5  Timer_A
        1. Table 5-27 Timer_A
      6. 5.8.6  eUSCI
        1. Table 5-28 eUSCI (UART Mode) Clock Frequency
        2. Table 5-29 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-30 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-31 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-32 eUSCI (SPI Slave Mode)
        6. Table 5-33 eUSCI (I2C Mode)
      7. 5.8.7  LCD Controller
        1. Table 5-34 LCD_C Recommended Operating Conditions
        2. Table 5-35 LCD_C Electrical Characteristics
      8. 5.8.8  SD24_B
        1. Table 5-36 SD24_B Power Supply and Recommended Operating Conditions
        2. Table 5-37 SD24_B Analog Input
        3. Table 5-38 SD24_B Supply Currents
        4. Table 5-39 SD24_B Performance
        5. Table 5-40 SD24_B AC Performance
        6. Table 5-41 SD24_B AC Performance
        7. Table 5-42 SD24_B AC Performance
        8. Table 5-43 SD24_B External Reference Input
      9. 5.8.9  ADC10_A
        1. Table 5-44 10-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-45 10-Bit ADC, Timing Parameters
        3. Table 5-46 10-Bit ADC, Linearity Parameters
        4. Table 5-47 10-Bit ADC, External Reference
      10. 5.8.10 REF
        1. Table 5-48 REF, Built-In Reference
      11. 5.8.11 Flash Memory
        1. Table 5-49 Flash Memory
      12. 5.8.12 Emulation and Debug
        1. Table 5-50 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagrams
    3. 6.3  CPU
    4. 6.4  Instruction Set
    5. 6.5  Operating Modes
    6. 6.6  Interrupt Vector Addresses
    7. 6.7  Memory Organization
    8. 6.8  Bootloader (BSL)
    9. 6.9  JTAG Operation
      1. 6.9.1 JTAG Standard Interface
      2. 6.9.2 Spy-Bi-Wire Interface
    10. 6.10 Flash Memory
    11. 6.11 RAM
    12. 6.12 Backup RAM
    13. 6.13 Peripherals
      1. 6.13.1  Oscillator and System Clock
      2. 6.13.2  Power Management Module (PMM)
      3. 6.13.3  Auxiliary Supply System (AUX)
      4. 6.13.4  Backup Subsystem
      5. 6.13.5  Digital I/O
      6. 6.13.6  Port Mapping Controller
      7. 6.13.7  System Module (SYS)
      8. 6.13.8  Watchdog Timer (WDT_A)
      9. 6.13.9  DMA Controller
      10. 6.13.10 CRC16
      11. 6.13.11 Hardware Multiplier
      12. 6.13.12 Enhanced Universal Serial Communication Interface (eUSCI)
      13. 6.13.13 ADC10_A
      14. 6.13.14 SD24_B
      15. 6.13.15 TA0
      16. 6.13.16 TA1
      17. 6.13.17 TA2
      18. 6.13.18 TA3
      19. 6.13.19 SD24_B Triggers
      20. 6.13.20 ADC10_A Triggers
      21. 6.13.21 Real-Time Clock (RTC_C)
      22. 6.13.22 Reference (REF) Module Voltage Reference
      23. 6.13.23 LCD_C
      24. 6.13.24 Embedded Emulation Module (EEM) (S Version)
      25. 6.13.25 Peripheral File Map
    14. 6.14 Input/Output Diagrams
      1. 6.14.1  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      2. 6.14.2  Port P1 (P1.2), Input/Output With Schmitt Trigger
      3. 6.14.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      4. 6.14.4  Port P1 (P1.6 and P1.7), Port P2 (P2.0 and P2.1) (PZ Package Only) Input/Output With Schmitt Trigger
      5. 6.14.5  Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (PZ Package Only)
      6. 6.14.6  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (PZ Package Only)
      7. 6.14.7  Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (PZ Package Only)
      8. 6.14.8  Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (PZ Package Only)
      9. 6.14.9  Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (PZ Package Only)
      10. 6.14.10 Port P9 (P9.0) Input/Output With Schmitt Trigger (PZ Package Only)
      11. 6.14.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (PZ Package Only)
      12. 6.14.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (PN Package Only)
      13. 6.14.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (PN Package Only)
      14. 6.14.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (PN Package Only)
      15. 6.14.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (PN Package Only)
      16. 6.14.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      17. 6.14.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    15. 6.15 Device Descriptors (TLV)
    16. 6.16 Identification
      1. 6.16.1 Revision Identification
      2. 6.16.2 Device Identification
      3. 6.16.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.13.25 Peripheral File Map

Table 6-18 lists the base address and offset address range for the registers of all supported peripherals.

Table 6-18 Peripherals

MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE
Special Functions (see Table 6-19) 0100h 000h to 01Fh
PMM (see Table 6-20) 0120h 000h to 01Fh
Flash Control (see Table 6-21) 0140h 000h to 00Fh
CRC16 (see Table 6-22) 0150h 000h to 007h
RAM Control (see Table 6-23) 0158h 000h to 001h
Watchdog (see Table 6-24) 015Ch 000h to 001h
UCS (see Table 6-25) 0160h 000h to 01Fh
SYS (see Table 6-26) 0180h 000h to 01Fh
Shared Reference (see Table 6-27) 01B0h 000h to 001h
Port Mapping Control (see Table 6-28) 01C0h 000h to 007h
Port Mapping Port P1 (see Table 6-29) 01C8h 000h to 007h
Port Mapping Port P2 (see Table 6-30) 01D0h 000h to 007h
Port Mapping Port P3 (see Table 6-31) 01D8h 000h to 007h
Port P1, P2 (see Table 6-32) 0200h 000h to 01Fh
Port P3, P4 (see Table 6-33) 0220h 000h to 00Bh
Port P5, P6 (see Table 6-34) 0240h 000h to 00Bh
Port P7, P8 (see Table 6-35)
(not available in PN package)		 0260h 000h to 00Bh
Port P9 (see Table 6-36)
(not available in PN package)		 0280h 000h to 00Bh
Port PJ (see Table 6-37) 0320h 000h to 01Fh
Timer TA0 (see Table 6-38) 0340h 000h to 03Fh
Timer TA1 (see Table 6-39) 0380h 000h to 03Fh
Timer TA2 (see Table 6-40) 0400h 000h to 03Fh
Timer TA3 (see Table 6-41) 0440h 000h to 03Fh
Backup Memory (see Table 6-42) 0480h 000h to 00Fh
RTC_C (see Table 6-43) 04A0h 000h to 01Fh
32-Bit Hardware Multiplier (see Table 6-44) 04C0h 000h to 02Fh
DMA General Control (see Table 6-45) 0500h 000h to 00Fh
DMA Channel 0 (see Table 6-46) 0500h 010h to 01Fh
DMA Channel 1 (see Table 6-47) 0500h 020h to 02Fh
DMA Channel 2 (see Table 6-48) 0500h 030h to 03Fh
eUSCI_A0 (see Table 6-49) 05C0h 000h to 01Fh
eUSCI_A1 (see Table 6-50) 05E0h 000h to 01Fh
eUSCI_A2 (see Table 6-51) 0600h 000h to 01Fh
eUSCI_B0 (see Table 6-52) 0640h 000h to 02Fh
ADC10_A (see Table 6-53) 0740h 000h to 01Fh
SD24_B(see Table 6-54) 0800h 000h to 06Fh
Auxiliary Supply (see Table 6-48) 09E0h 000h to 01Fh
LCD_C (see Table 6-56) 0A00h 000h to 05Fh

Table 6-19 Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION REGISTER OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h

Table 6-20 PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION REGISTER OFFSET
PMM control 0 PMMCTL0 00h
PMM control 1 PMMCTL1 02h
SVS high-side control SVSMHCTL 04h
SVS low-side control SVSMLCTL 06h
PMM interrupt flags PMMIFG 0Ch
PMM interrupt enable PMMIE 0Eh
PMM power mode 5 control register 0 PM5CTL0 10h

Table 6-21 Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION REGISTER OFFSET
Flash control 1 FCTL1 00h
Flash control 3 FCTL3 04h
Flash control 4 FCTL4 06h

Table 6-22 CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION REGISTER OFFSET
CRC data input CRC16DI 00h
CRC data input reverse byte CRC16DIRB 02h
CRC result CRCINIRES 04h
CRC result reverse byte CRCRESR 06h

Table 6-23 RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION REGISTER OFFSET
RAM control 0 RCCTL0 00h

Table 6-24 Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION REGISTER OFFSET
Watchdog timer control WDTCTL 00h

Table 6-25 UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION REGISTER OFFSET
UCS control 0 UCSCTL0 00h
UCS control 1 UCSCTL1 02h
UCS control 2 UCSCTL2 04h
UCS control 3 UCSCTL3 06h
UCS control 4 UCSCTL4 08h
UCS control 5 UCSCTL5 0Ah
UCS control 6 UCSCTL6 0Ch
UCS control 7 UCSCTL7 0Eh
UCS control 8 UCSCTL8 10h

Table 6-26 SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION REGISTER OFFSET
System control SYSCTL 00h
Bootloader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
Bus error vector generator SYSBERRIV 18h
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh

Table 6-27 Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION REGISTER OFFSET
Shared reference control REFCTL 00h

Table 6-28 Port Mapping Controller (Base Address: 01C0h)

REGISTER DESCRIPTION REGISTER OFFSET
Port mapping password PMAPPWD 00h
Port mapping control PMAPCTL 02h

Table 6-29 Port Mapping for Port P1 (Base Address: 01C8h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P1.0 mapping P1MAP0 00h
Port P1.1 mapping P1MAP1 01h
Port P1.2 mapping P1MAP2 02h
Port P1.3 mapping P1MAP3 03h
Port P1.4 mapping P1MAP4 04h
Port P1.5 mapping P1MAP5 05h
Port P1.6 mapping P1MAP6 06h
Port P1.7 mapping P1MAP7 07h

Table 6-30 Port Mapping for Port P2 (Base Address: 01D0h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P2.0 mapping P2MAP0 00h
Port P2.1 mapping P2MAP2 01h
Port P2.2 mapping P2MAP2 02h
Port P2.3 mapping P2MAP3 03h
Port P2.4 mapping P2MAP4 04h
Port P2.5 mapping P2MAP5 05h
Port P2.6 mapping P2MAP6 06h
Port P2.7 mapping P2MAP7 07h

Table 6-31 Port Mapping for Port P3 (Base Address: 01D8h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P3.0 mapping P3MAP0 00h
Port P3.1 mapping P3MAP3 01h
Port P3.2 mapping P3MAP2 02h
Port P3.3 mapping P3MAP3 03h
Port P3.4 mapping P3MAP4 04h
Port P3.5 mapping P3MAP5 05h
Port P3.6 mapping P3MAP6 06h
Port P3.7 mapping P3MAP7 07h

Table 6-32 Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 resistor enable P1REN 06h
Port P1 drive strength P1DS 08h
Port P1 selection P1SEL 0Ah
Port P1 interrupt vector word P1IV 0Eh
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 input P2IN 01h
Port P2 output P2OUT 03h
Port P2 direction P2DIR 05h
Port P2 resistor enable P2REN 07h
Port P2 drive strength P2DS 09h
Port P2 selection P2SEL 0Bh
Port P2 interrupt vector word P2IV 1Eh
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt flag P2IFG 1Dh

Table 6-33 Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P3 input P3IN 00h
Port P3 output P3OUT 02h
Port P3 direction P3DIR 04h
Port P3 resistor enable P3REN 06h
Port P3 drive strength P3DS 08h
Port P3 selection P3SEL 0Ah
Port P4 input P4IN 01h
Port P4 output P4OUT 03h
Port P4 direction P4DIR 05h
Port P4 resistor enable P4REN 07h
Port P4 drive strength P4DS 09h
Port P4 selection P4SEL 0Bh

Table 6-34 Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P5 input P5IN 00h
Port P5 output P5OUT 02h
Port P5 direction P5DIR 04h
Port P5 resistor enable P5REN 06h
Port P5 drive strength P5DS 08h
Port P5 selection P5SEL 0Ah
Port P6 input P6IN 01h
Port P6 output P6OUT 03h
Port P6 direction P6DIR 05h
Port P6 resistor enable P6REN 07h
Port P6 drive strength P6DS 09h
Port P6 selection P6SEL 0Bh

Table 6-35 Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P7 input P7IN 00h
Port P7 output P7OUT 02h
Port P7 direction P7DIR 04h
Port P7 resistor enable P7REN 06h
Port P7 drive strength P7DS 08h
Port P7 selection P7SEL 0Ah
Port P8 input P8IN 01h
Port P8 output P8OUT 03h
Port P8 direction P8DIR 05h
Port P8 resistor enable P8REN 07h
Port P8 drive strength P8DS 09h
Port P8 selection P8SEL 0Bh

Table 6-36 Port P9 Registers (Base Address: 0280h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P9 input P9IN 00h
Port P9 output P9OUT 02h
Port P9 direction P9DIR 04h
Port P9 resistor enable P9REN 06h
Port P9 drive strength P9DS 08h
Port P9 selection P9SEL 0Ah

Table 6-37 Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION REGISTER OFFSET
Port PJ input PJIN 00h
Port PJ output PJOUT 02h
Port PJ direction PJDIR 04h
Port PJ resistor enable PJREN 06h
Port PJ drive strength PJDS 08h
Port PJ selection PJSEL 0Ah

Table 6-38 TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION REGISTER OFFSET
TA0 control TA0CTL 00h
Capture/compare control 0 TA0CCTL0 02h
Capture/compare control 1 TA0CCTL1 04h
Capture/compare control 2 TA0CCTL2 06h
TA0 counter TA0R 10h
Capture/compare 0 TA0CCR0 12h
Capture/compare 1 TA0CCR1 14h
Capture/compare 2 TA0CCR2 16h
TA0 expansion 0 TA0EX0 20h
TA0 interrupt vector TA0IV 2Eh

Table 6-39 TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION REGISTER OFFSET
TA1 control TA1CTL 00h
Capture/compare control 0 TA1CCTL0 02h
Capture/compare control 1 TA1CCTL1 04h
TA1 counter TA1R 10h
Capture/compare 0 TA1CCR0 12h
Capture/compare 1 TA1CCR1 14h
TA1 expansion 0 TA1EX0 20h
TA1 interrupt vector TA1IV 2Eh

Table 6-40 TA2 Registers (Base Address: 0400h)

REGISTER DESCRIPTION REGISTER OFFSET
TA2 control TA2CTL 00h
Capture/compare control 0 TA2CCTL0 02h
Capture/compare control 1 TA2CCTL1 04h
TA2 counter TA2R 10h
Capture/compare 0 TA2CCR0 12h
Capture/compare 1 TA2CCR1 14h
TA2 expansion 0 TA2EX0 20h
TA2 interrupt vector TA2IV 2Eh

Table 6-41 TA3 Registers (Base Address: 0440h)

REGISTER DESCRIPTION REGISTER OFFSET
TA3 control TA3CTL 00h
Capture/compare control 0 TA3CCTL0 02h
Capture/compare control 1 TA3CCTL1 04h
TA3 counter TA3R 10h
Capture/compare 0 TA3CCR0 12h
Capture/compare 1 TA3CCR1 14h
TA3 expansion 0 TA3EX0 20h
TA3 interrupt vector TA3IV 2Eh

Table 6-42 Backup Memory Registers (Base Address: 0480h)

REGISTER DESCRIPTION REGISTER OFFSET
Backup memory 0 BAKMEM0 00h
Backup memory 1 BAKMEM1 02h
Backup memory 2 BAKMEM2 04h
Backup memory 3 BAKMEM3 06h

Table 6-43 RTC_C Registers (Base Address: 04A0h)

REGISTER DESCRIPTION REGISTER OFFSET
RTC control 0 RTCCTL0 00h
RTC password RTCPWD 01h
RTC control 1 RTCCTL1 02h
RTC control 3 RTCCTL3 03h
RTC offset calibration RTCOCAL 04h
RTC temperature compensation RTCTCMP 06h
RTC prescaler 0 control RTCPS0CTL 08h
RTC prescaler 1 control RTCPS1CTL 0Ah
RTC prescaler 0 RTCPS0 0Ch
RTC prescaler 1 RTCPS1 0Dh
RTC interrupt vector word RTCIV 0Eh
RTC seconds RTCSEC 10h
RTC minutes RTCMIN 11h
RTC hours RTCHOUR 12h
RTC day of week RTCDOW 13h
RTC days RTCDAY 14h
RTC month RTCMON 15h
RTC year RTCYEAR 16h
RTC alarm minutes RTCAMIN 18h
RTC alarm hours RTCAHOUR 19h
RTC alarm day of week RTCADOW 1Ah
RTC alarm days RTCADAY 1Bh
Binary-to-BCD conversion BIN2BCD 1Ch
BCD-to-binary conversion BCD2BIN 1Eh

Table 6-44 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION REGISTER OFFSET
16-bit operand 1 – multiply MPY 00h
16-bit operand 1 – signed multiply MPYS 02h
16-bit operand 1 – multiply accumulate MAC 04h
16-bit operand 1 – signed multiply accumulate MACS 06h
16-bit operand 2 OP2 08h
16 × 16 result low word RESLO 0Ah
16 × 16 result high word RESHI 0Ch
16 × 16 sum extension SUMEXT 0Eh
32-bit operand 1 – multiply low word MPY32L 10h
32-bit operand 1 – multiply high word MPY32H 12h
32-bit operand 1 – signed multiply low word MPYS32L 14h
32-bit operand 1 – signed multiply high word MPYS32H 16h
32-bit operand 1 – multiply accumulate low word MAC32L 18h
32-bit operand 1 – multiply accumulate high word MAC32H 1Ah
32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 – low word OP2L 20h
32-bit operand 2 – high word OP2H 22h
32 × 32 result 0 – least significant word RES0 24h
32 × 32 result 1 RES1 26h
32 × 32 result 2 RES2 28h
32 × 32 result 3 – most significant word RES3 2Ah
MPY32 control 0 MPY32CTL0 2Ch

Table 6-45 DMA General Control Registers (Base Address: 0500h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA module control 0 DMACTL0 00h
DMA module control 1 DMACTL1 02h
DMA module control 2 DMACTL2 04h
DMA module control 3 DMACTL3 06h
DMA module control 4 DMACTL4 08h
DMA interrupt vector DMAIV 0Eh

Table 6-46 DMA Channel 0 Registers (Base Address: 0500h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 0 control DMA0CTL 10h
DMA channel 0 source address low DMA0SAL 12h
DMA channel 0 source address high DMA0SAH 14h
DMA channel 0 destination address low DMA0DAL 16h
DMA channel 0 destination address high DMA0DAH 18h
DMA channel 0 transfer size DMA0SZ 1Ah

Table 6-47 DMA Channel 1 Registers (Base Address: 0500h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 1 control DMA1CTL 20h
DMA channel 1 source address low DMA1SAL 22h
DMA channel 1 source address high DMA1SAH 24h
DMA channel 1 destination address low DMA1DAL 26h
DMA channel 1 destination address high DMA1DAH 28h
DMA channel 1 transfer size DMA1SZ 2Ah

Table 6-48 DMA Channel 2 Registers (Base Address: 0500h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 2 control DMA2CTL 30h
DMA channel 2 source address low DMA2SAL 32h
DMA channel 2 source address high DMA2SAH 34h
DMA channel 2 destination address low DMA2DAL 36h
DMA channel 2 destination address high DMA2DAH 38h
DMA channel 2 transfer size DMA2SZ 3Ah

Table 6-49 eUSCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_A control word 0 UCA0CTLW0 00h
eUSCI _A control word 1 UCA0CTLW1 02h
eUSCI_A baud rate 0 UCA0BR0 06h
eUSCI_A baud rate 1 UCA0BR1 07h
eUSCI_A modulation control UCA0MCTLW 08h
eUSCI_A status UCA0STAT 0Ah
eUSCI_A receive buffer UCA0RXBUF 0Ch
eUSCI_A transmit buffer UCA0TXBUF 0Eh
eUSCI_A LIN control UCA0ABCTL 10h
eUSCI_A IrDA transmit control UCA0IRTCTL 12h
eUSCI_A IrDA receive control UCA0IRRCTL 13h
eUSCI_A interrupt enable UCA0IE 1Ah
eUSCI_A interrupt flags UCA0IFG 1Ch
eUSCI_A interrupt vector word UCA0IV 1Eh

Table 6-50 eUSCI_A1 Registers (Base Address:05E0h)

REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_A control word 0 UCA1CTLW0 00h
eUSCI _A control word 1 UCA1CTLW1 02h
eUSCI_A baud rate 0 UCA1BR0 06h
eUSCI_A baud rate 1 UCA1BR1 07h
eUSCI_A modulation control UCA1MCTLW 08h
eUSCI_A status UCA1STAT 0Ah
eUSCI_A receive buffer UCA1RXBUF 0Ch
eUSCI_A transmit buffer UCA1TXBUF 0Eh
eUSCI_A LIN control UCA1ABCTL 10h
eUSCI_A IrDA transmit control UCA1IRTCTL 12h
eUSCI_A IrDA receive control UCA1IRRCTL 13h
eUSCI_A interrupt enable UCA1IE 1Ah
eUSCI_A interrupt flags UCA1IFG 1Ch
eUSCI_A interrupt vector word UCA1IV 1Eh

Table 6-51 eUSCI_A2 Registers (Base Address:0600h)

REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_A control word 0 UCA2CTLW0 00h
eUSCI _A control word 1 UCA2CTLW1 02h
eUSCI_A baud rate 0 UCA2BR0 06h
eUSCI_A baud rate 1 UCA2BR1 07h
eUSCI_A modulation control UCA2MCTLW 08h
eUSCI_A status UCA2STAT 0Ah
eUSCI_A receive buffer UCA2RXBUF 0Ch
eUSCI_A transmit buffer UCA2TXBUF 0Eh
eUSCI_A LIN control UCA2ABCTL 10h
eUSCI_A IrDA transmit control UCA2IRTCTL 12h
eUSCI_A IrDA receive control UCA2IRRCTL 13h
eUSCI_A interrupt enable UCA2IE 1Ah
eUSCI_A interrupt flags UCA2IFG 1Ch
eUSCI_A interrupt vector word UCA2IV 1Eh

Table 6-52 eUSCI_B0 Registers (Base Address: 0640h)

REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_B control word 0 UCB0CTLW0 00h
eUSCI_B control word 1 UCB0CTLW1 02h
eUSCI_B bit rate 0 UCB0BR0 06h
eUSCI_B bit rate 1 UCB0BR1 07h
eUSCI_B status word UCB0STATW 08h
eUSCI_B byte counter threshold UCB0TBCNT 0Ah
eUSCI_B receive buffer UCB0RXBUF 0Ch
eUSCI_B transmit buffer UCB0TXBUF 0Eh
eUSCI_B I2C own address 0 UCB0I2COA0 14h
eUSCI_B I2C own address 1 UCB0I2COA1 16h
eUSCI_B I2C own address 2 UCB0I2COA2 18h
eUSCI_B I2C own address 3 UCB0I2COA3 1Ah
eUSCI_B received address UCB0ADDRX 1Ch
eUSCI_B address mask UCB0ADDMASK 1Eh
eUSCI I2C slave address UCB0I2CSA 20h
eUSCI interrupt enable UCB0IE 2Ah
eUSCI interrupt flags UCB0IFG 2Ch
eUSCI interrupt vector word UCB0IV 2Eh

Table 6-53 ADC10_A Registers (Base Address: 0740h)

REGISTER DESCRIPTION REGISTER OFFSET
ADC10_A control 0 ADC10CTL0 00h
ADC10_A control 1 ADC10CTL1 02h
ADC10_A control 2 ADC10CTL2 04h
ADC10_A window comparator low threshold ADC10LO 06h
ADC10_A window comparator high threshold ADC10HI 08h
ADC10_A memory control 0 ADC10MCTL0 0Ah
ADC10_A conversion memory ADC10MCTL0 12h
ADC10_A interrupt enable ADC10IE 1Ah
ADC10_A interrupt flags ADC10IGH 1Ch
ADC10_A interrupt vector word ADC10IV 1Eh

Table 6-54 SD24_B Registers (Base Address: 0800h)

REGISTER DESCRIPTION REGISTER OFFSET
SD24_B control 0 SD24BCTL0 00h
SD24_B control 1 SD24BCTL1 02h
SD24_B trigger control SD24BTRGCTL 04h
SD24_B trigger OSR control SD24BTRGOSR 06h
SD24_B trigger preload SD24BTRGPRE 08h
SD24_B interrupt flag SD24BIFG 0Ah
SD24_B interrupt enable SD24BIE 0Ch
SD24_B interrupt vector SD24BIV 0Eh
SD24_B converter 0 control SD24BCCTL0 10h
SD24_B converter 0 input control SD24BINCTL0 12h
SD24_B converter 0 OSR control SD24BOSR0 14h
SD24_B converter 0 preload SD24BPRE0 16h
SD24_B converter 1 control SD24BCCTL1 18h
SD24_B converter 1 input control SD24BINCTL1 1Ah
SD24_B converter 1 OSR control SD24BOSR1 1Ch
SD24_B converter 1 preload SD24BPRE1 1Eh
SD24_B converter 2 control SD24BCCTL2 20h
SD24_B converter 2 input control SD24BINCTL2 22h
SD24_B converter 2 OSR control SD24BOSR2 24h
SD24_B converter 2 preload SD24BPRE2 26h
SD24_B converter 0 conversion memory low word SD24BMEML0 50h
SD24_B converter 0 conversion memory high word SD24BMEMH0 52h
SD24_B converter 1 conversion memory low word SD24BMEML1 54h
SD24_B converter 1 conversion memory high word SD24BMEMH1 56h
SD24_B converter 2 conversion memory low word SD24BMEML2 58h
SD24_B converter 2 conversion memory high word SD24BMEMH2 5Ah

Table 6-55 Auxiliary Supplies Registers (Base Address: 09E0h)

REGISTER DESCRIPTION REGISTER OFFSET
Auxiliary supply control 0 AUXCTL0 00h
Auxiliary supply control 1 AUXCTL1 02h
Auxiliary supply control 2 AUXCTL2 04h
AUX2 charger control AUX2CHCTL 12h
AUX3 charger control AUX3CHCTL 14h
AUX ADC control AUXADCCTL 16h
AUX interrupt flag AUXIFG 1Ah
AUX interrupt enable AUXIE 1Ch
AUX interrupt vector word AUXIV 1Eh

Table 6-56 LCD_C Registers (Base Address: 0A00h)

REGISTER DESCRIPTION REGISTER OFFSET
LCD_C control 0 LCDCCTL0 000h
LCD_C control 1 LCDCCTL1 002h
LCD_C blinking control LCDCBLKCTL 004h
LCD_C memory control LCDCMEMCTL 006h
LCD_C voltage control LCDCVCTL 008h
LCD_C port control 0 LCDCPCTL0 00Ah
LCD_C port control 1 LCDCPCTL1 00Ch
LCD_C port control 2 LCDCPCTL2 00Eh
LCD_C charge pump control LCDCCPCTL 012h
LCD_C interrupt vector LCDCIV 01Eh
Static and 2 to 4 mux modes
LCD_C memory 1 LCDM1 020h
LCD_C memory 2 LCDM2 021h
  ⋮   ⋮   ⋮
LCD_C memory 20 LCDM20 033h
LCD_C blinking memory 1 LCDBM1 040h
LCD_C blinking memory 2 LCDBM2 041h
  ⋮   ⋮   ⋮
LCD_C blinking memory 20 LCDBM20 053h
5 to 8 mux modes
LCD_C memory 1 LCDM1 020h
LCD_C memory 2 LCDM2 021h
  ⋮   ⋮   ⋮
LCD_C memory 40 LCDM40 047h