SLASE50A February 2015 – October 2018 MSP430F67621A , MSP430F67641A
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
AVCC | Analog supply voltage | AVCC and DVCC are connected together,
AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V |
1.8 | 3.6 | V | ||
V(Ax) | Analog input voltage range(1) | All ADC10_A pins | 0 | AVCC | V | ||
IADC10_A | Operating supply current into AVCC terminal, REF module and reference buffer off | fADC10CLK = 5 MHz, ADC10ON =1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 00 |
2.2 V | 70 | 105 | µA | |
3 V | 80 | 115 | |||||
Operating supply current into AVCC terminal, REF module on, reference buffer on | fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 01 |
3 V | 130 | 185 | |||
Operating supply current into AVCC terminal, REF module off, reference buffer on | fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 10, VEREF = 2.5 V |
3 V | 108 | 160 | |||
Operating supply current into AVCC terminal, REF module off, reference buffer off | fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 11, VEREF = 2.5 V |
3 V | 74 | 105 | |||
CI | Input capacitance | Only one terminal Ax can be selected at one time from the pad to the ADC10_A capacitor array including wiring and pad. | 2.2 V | 3.5 | pF | ||
RI | Input MUX ON resistance | AVCC > 2 V, 0 V ≤ VAx ≤ AVCC | 36 | kΩ | |||
1.8 V < AVCC < 2 V, 0 V ≤ VAx ≤ AVCC | 96 |
Table 5-44 lists the timing parameters of the ADC.