SLAS768E September   2012  – September 2018 MSP430F6745 , MSP430F6746 , MSP430F6747 , MSP430F6748 , MSP430F6749 , MSP430F6765 , MSP430F6766 , MSP430F6767 , MSP430F6768 , MSP430F6769 , MSP430F6775 , MSP430F6776 , MSP430F6777 , MSP430F6778 , MSP430F6779

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Application Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-3 Terminal Functions – PEU Package
      2. Table 4-4 Terminal Functions – PZ Package
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Thermal Packaging Characteristics
    8. 5.8  Schmitt-Trigger Inputs – General-Purpose I/O
    9. 5.9  Inputs – Ports P1 and P2
    10. 5.10 Leakage Current – General-Purpose I/O
    11. 5.11 Outputs – General-Purpose I/O (Full Drive Strength)
    12. 5.12 Outputs – General-Purpose I/O (Reduced Drive Strength)
    13. 5.13 Output Frequency – General-Purpose I/O
    14. 5.14 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    15. 5.15 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    16. 5.16 Crystal Oscillator, XT1, Low-Frequency Mode
    17. 5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 5.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 5.19 DCO Frequency
    20. 5.20 PMM, Brownout Reset (BOR)
    21. 5.21 PMM, Core Voltage
    22. 5.22 PMM, SVS High Side
    23. 5.23 PMM, SVM High Side
    24. 5.24 PMM, SVS Low Side
    25. 5.25 PMM, SVM Low Side
    26. 5.26 Wake-up Times From Low-Power Modes and Reset
    27. 5.27 Auxiliary Supplies Recommended Operating Conditions
    28. 5.28 Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents
    29. 5.29 Auxiliary Supplies, Auxiliary Supply Monitor
    30. 5.30 Auxiliary Supplies, Switch ON-Resistance
    31. 5.31 Auxiliary Supplies, Switching Time
    32. 5.32 Auxiliary Supplies, Switch Leakage
    33. 5.33 Auxiliary Supplies, Auxiliary Supplies to ADC10_A
    34. 5.34 Auxiliary Supplies, Charge Limiting Resistor
    35. 5.35 Timer_A
    36. 5.36 eUSCI (UART Mode) Clock Frequency
    37. 5.37 eUSCI (UART Mode)
    38. 5.38 eUSCI (SPI Master Mode) Clock Frequency
    39. 5.39 eUSCI (SPI Master Mode)
    40. 5.40 eUSCI (SPI Slave Mode)
    41. 5.41 eUSCI (I2C Mode)
    42. 5.42 Schmitt-Trigger Inputs, RTC Tamper Detect Pin
    43. 5.43 Inputs, RTC Tamper Detect Pin
    44. 5.44 Leakage Current, RTC Tamper Detect Pin
    45. 5.45 Outputs, RTC Tamper Detect Pin
    46. 5.46 LCD_C Recommended Operating Conditions
    47. 5.47 LCD_C Electrical Characteristics
    48. 5.48 SD24_B Power Supply and Recommended Operating Conditions
    49. 5.49 SD24_B Analog Input
    50. 5.50 SD24_B Supply Currents
    51. 5.51 SD24_B Performance
    52. 5.52 SD24_B, AC Performance
    53. 5.53 SD24_B, AC Performance
    54. 5.54 SD24_B, AC Performance
    55. 5.55 SD24_B External Reference Input
    56. 5.56 10-Bit ADC Power Supply and Input Range Conditions
    57. 5.57 10-Bit ADC Switching Characteristics
    58. 5.58 10-Bit ADC Linearity Parameters
    59. 5.59 10-Bit ADC External Reference
    60. 5.60 REF Built-In Reference
    61. 5.61 Comparator_B
    62. 5.62 Flash Memory
    63. 5.63 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Functional Block Diagrams
    2. 6.2  CPU (Link to User's Guide)
    3. 6.3  Instruction Set
    4. 6.4  Operating Modes
    5. 6.5  Interrupt Vector Addresses
    6. 6.6  Special Function Registers (SFRs)
      1. Table 6-4 Interrupt Enable 1 Register Description
      2. Table 6-5 Interrupt Flag 1 Register Description
    7. 6.7  Memory Organization
    8. 6.8  Bootloader (BSL)
    9. 6.9  JTAG Operation
      1. 6.9.1 JTAG Standard Interface
      2. 6.9.2 Spy-Bi-Wire Interface
    10. 6.10 Flash Memory (Link to User's Guide)
    11. 6.11 RAM (Link to User's Guide)
    12. 6.12 Backup RAM (Link to User's Guide)
    13. 6.13 Peripherals
      1. 6.13.1  Oscillator and System Clock (Link to User's Guide)
      2. 6.13.2  Power-Management Module (PMM) (Link to User's Guide)
      3. 6.13.3  Auxiliary Supply System (Link to User's Guide)
      4. 6.13.4  Backup Subsystem
      5. 6.13.5  Digital I/O (Link to User's Guide)
      6. 6.13.6  Port Mapping Controller (Link to User's Guide)
      7. 6.13.7  System Module (SYS) (Link to User's Guide)
      8. 6.13.8  Watchdog Timer (WDT_A) (Link to User's Guide)
      9. 6.13.9  DMA Controller (Link to User's Guide)
      10. 6.13.10 CRC16 (Link to User's Guide)
      11. 6.13.11 Hardware Multiplier (Link to User's Guide)
      12. 6.13.12 AES128 Accelerator (Link to User's Guide)
      13. 6.13.13 Enhanced Universal Serial Communication Interface (eUSCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      14. 6.13.14 ADC10_A (Link to User's Guide)
      15. 6.13.15 SD24_B (Link to User's Guide)
      16. 6.13.16 TA0 (Link to User's Guide)
      17. 6.13.17 TA1 (Link to User's Guide)
      18. 6.13.18 TA2 (Link to User's Guide)
      19. 6.13.19 TA3 (Link to User's Guide)
      20. 6.13.20 SD24_B Triggers
      21. 6.13.21 ADC10_A Triggers
      22. 6.13.22 Real-Time Clock (RTC_C) (Link to User's Guide)
      23. 6.13.23 Reference Module (REF) Voltage Reference (Link to User's Guide)
      24. 6.13.24 LCD_C (Link to User's Guide)
      25. 6.13.25 Comparator_B (Link to User's Guide)
      26. 6.13.26 Embedded Emulation Module (EEM) (Link to User's Guide)
      27. 6.13.27 Peripheral File Map
    14. 6.14 Input/Output Diagrams
      1. 6.14.1  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      2. 6.14.2  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      3. 6.14.3  Port P1 (P1.4 and P1.5) Input/Output With Schmitt Trigger (MSP430F677xIPEU and MSP430F677xIPZ)
      4. 6.14.4  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU and MSP430F677xIPZ)
      5. 6.14.5  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      6. 6.14.6  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      7. 6.14.7  Port P2 (P2.4 and P2.6) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      8. 6.14.8  Port P2 (P2.7) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      9. 6.14.9  Ports P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      10. 6.14.10 Ports P3 (P3.0) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      11. 6.14.11 Ports P3 (P3.1 to P3.7) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      12. 6.14.12 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      13. 6.14.13 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      14. 6.14.14 Port P5 (P5.0 to P5.3) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      15. 6.14.15 Port P5 (P5.4 to P5.6) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      16. 6.14.16 Port P5 (P5.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      17. 6.14.17 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      18. 6.14.18 Port P6 (P6.0) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      19. 6.14.19 Port P6 (P6.1 to P6.3) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      20. 6.14.20 Port P6 (P6.4 to P6.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      21. 6.14.21 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      22. 6.14.22 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger (MSP430F67xxIPEU Only)
      23. 6.14.23 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      24. 6.14.24 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      25. 6.14.25 Port P8 (P8.0) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      26. 6.14.26 Port P8 (P8.1) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      27. 6.14.27 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      28. 6.14.28 Port P10 (P10.0 to P10.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      29. 6.14.29 Port P11 (P11.0) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      30. 6.14.30 Port P11 (P11.1) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      31. 6.14.31 Port P11 (P11.2 and P11.3) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      32. 6.14.32 Port P11 (P11.4 and P11.5) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      33. 6.14.33 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      34. 6.14.34 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    15. 6.15 Device Descriptors (TLV)
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.12 Backup RAM (Link to User's Guide)

The backup RAM provides a limited number of bytes of RAM that are retained during LPM3.5. This backup RAM is part of the backup subsystem that operates on dedicated power supply AUXVCC3. Eight bytes of backup RAM are available in this device. The backup RAM can be word-wise accessed through the registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3. The backup RAM registers cannot be accessed by CPU when the high-side SVS is disabled by the user application.