SLAS983 Data sheet

SLAS983A May 2014 – September 2018 MSP430F67451A , MSP430F67461A , MSP430F67471A , MSP430F67481A , MSP430F67491A , MSP430F67651A , MSP430F67661A , MSP430F67671A , MSP430F67681A , MSP430F67691A , MSP430F67751A , MSP430F67761A , MSP430F67771A , MSP430F67781A , MSP430F67791A

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

PEU|128
- MPQF058B
PZ|100
- MTQF013A

Thermal pad, mechanical data (Package|Pins)

PZ|100
- QFND428

Orderable Information

Table 5-42 SD24_B, Performance

f_SD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
INL	Integral nonlinearity, end-point fit	SD24GAIN: 1	3 V	–0.01		+0.01	% of FSR
		SD24GAIN: 8		–0.01		+0.01
		SD24GAIN: 32		–0.01		+0.01
G_nom	Nominal gain	SD24GAIN: 1	3 V		1
		SD24GAIN: 2			2
		SD24GAIN: 4			4
		SD24GAIN: 8			8
		SD24GAIN: 16			16
		SD24GAIN: 32			32
		SD24GAIN: 64			64
		SD24GAIN: 128			128
E_G	Gain error⁽¹⁾	SD24GAIN: 1, with external reference (1.2 V)	3 V	–1%		+1%
		SD24GAIN: 8, with external reference (1.2 V)		–2%		+2%
		SD24GAIN: 32, with external reference (1.2 V)		–2%		+2%
ΔE_G/ΔT	Gain error temperature coefficient⁽²⁾, internal reference	SD24GAIN: 1, 8, or 32 (with internal reference)	3 V			80	ppm/°C
ΔE_G/ΔT	Gain error temperature coefficient⁽²⁾, external reference	SD24GAIN: 1 (with external reference)	3 V			15	ppm/°C
		SD24GAIN: 8 (with external reference)				15
		SD24GAIN: 32 (with external reference)				15
ΔE_G/ΔV_CC	Gain error vs V_CC⁽³⁾	SD24GAIN: 1	3 V		0.1		%/V
		SD24GAIN: 8			0.1
		SD24GAIN: 32			0.4
E_OS[V]	Offset error⁽⁴⁾	SD24GAIN: 1 (with Vdiff = 0 V)	3 V			2.3	mV
		SD24GAIN: 8				1
		SD24GAIN: 32				0.5
E_OS[FS]	Offset error⁽⁴⁾	SD24GAIN: 1 (with Vdiff = 0 V)	3 V	–0.2		+0.2	% FS
		SD24GAIN: 8		–0.7		+0.7
		SD24GAIN: 32		–1.4		+1.4
ΔE_OS/ΔT	Offset error temperature coefficient⁽⁵⁾	SD24GAIN: 1	3 V		2		µV/°C
		SD24GAIN: 8			0.25
		SD24GAIN: 32			0.1
ΔE_OS/ΔV_CC	Offset error vs V_CC⁽⁶⁾	SD24GAIN: 1	3 V		500		µV/V
		SD24GAIN: 8			125
		SD24GAIN: 32			50
CMRR,DC	Common-mode rejection at DC⁽⁷⁾	SD24GAIN: 1	3 V		–120		dB
		SD24GAIN: 8			–110
		SD24GAIN: 32			–100
CMRR,50Hz	Common-mode rejection at 50 Hz⁽⁸⁾	SD24GAIN: 1, f_CM = 50 Hz, V_CM = 930 mV	3 V		–120		dB
		SD24GAIN: 8, f_CM = 50 Hz, V_CM = 120 mV			–110
		SD24GAIN: 32, f_CM = 50 Hz, V_CM = 30 mV			–100
AC PSRR, ext	AC power supply rejection ratio, external reference⁽⁹⁾	SD24GAIN: 1, V_CC = 3 V + 50 mV × sin(2π × f_VCC × t), f_VCC = 50 Hz			–61		dB
		SD24GAIN: 8, V_CC = 3 V + 50 mV × sin(2π × f_VCC × t), f_VCC = 50 Hz			–75
		SD24GAIN: 32, V_CC = 3 V + 50 mV × sin(2π × f_VCC × t), f_VCC = 50 Hz			–79
AC PSRR, int	AC power supply rejection ratio, internal reference⁽⁹⁾	SD24GAIN: 1, V_CC = 3 V + 50 mV × sin(2π × f_VCC × t), f_VCC = 50 Hz			–61		dB
		SD24GAIN: 8, V_CC = 3 V + 50 mV × sin(2π × f_VCC × t), f_VCC = 50 Hz			–75
		SD24GAIN: 32, V_CC = 3 V + 50 mV × sin(2π × f_VCC × t), f_VCC = 50 Hz			–79
XT	Crosstalk between converters⁽¹⁰⁾	Crosstalk source: SD24GAIN: 1, Sine-wave with maximum possible Vpp, f_IN = 50 Hz or 100 Hz, Converter under test: SD24GAIN: 1	3 V		–120		dB
		Crosstalk source: SD24GAIN: 1, Sine-wave with maximum possible Vpp, f_IN = 50 Hz or 100 Hz, Converter under test: SD24GAIN: 8			–115
		Crosstalk source: SD24GAIN: 1, Sine-wave with maximum possible Vpp, f_IN = 50 Hz or 100 Hz, Converter under test: SD24GAIN: 32			–110

(1) The gain error E_G specifies the deviation of the actual gain G_act from the nominal gain G_nom: E_G = (G_act – G_nom)/G_nom. It covers process, temperature, and supply voltage variations.

(2) The gain error temperature coefficient ΔE_G/ ΔT specifies the variation of the gain error E_G over temperature (E_G(T) = (G_act(T) – G_nom)/G_nom) using the box method (that is, minimum and maximum values):
ΔE_G/ ΔT = (MAX(E_G(T)) – MIN(E_G(T) ) / (MAX(T) – MIN(T)) = (MAX(G_act(T)) – MIN(G_act(T)) / G_nom / (MAX(T) – MIN(T))
with T ranging from –40°C to 85°C.

(3) The gain error vs V_CC coefficient ΔE_G/ ΔV_CC specifies the variation of the gain error E_G over supply voltage (E_G(V_CC) = (G_act(V_CC) – G_nom)/G_nom) using the box method (that is, minimum and maximum values):
ΔE_G/ ΔV_CC = (MAX(E_G(V_CC)) – MIN(E_G(V_CC) ) / (MAX(V_CC) – MIN(V_CC)) = (MAX(G_act(V_CC)) – MIN(G_act(V_CC)) / G_nom / (MAX(V_CC) – MIN(V_CC))
with V_CC ranging from 2.4 V to 3.6 V.

(4) The offset error E_OS is measured with shorted inputs in 2s-complement mode with +100% FS = V_REF/G and –100% FS = –V_REF/G.
Conversion between E_OS [FS] and E_OS [V] is as follows: E_OS [FS] = E_OS [V] × G/V_REF, E_OS [V] = E_OS [FS] × V_REF/G.

(5) The offset error temperature coefficient ΔE_OS/ ΔT specifies the variation of the offset error E_OS over temperature using the box method (that is, minimum and maximum values):
ΔE_OS/ ΔT = (MAX(E_OS(T)) – MIN(E_OS(T) ) / (MAX(T) – MIN(T))
with T ranging from –40°C to 85°C.

(6) The offset error vs V_CC ΔE_OS/ ΔV_CC specifies the variation of the offset error E_OS over supply voltage using the box method (that is, minimum and maximum values):
ΔE_OS/ ΔV_CC = (MAX(E_OS(V_CC)) – MIN(E_OS(V_CC) ) / (MAX(V_CC) – MIN(V_CC))
with V_CC ranging from 2.4 V to 3.6 V.

(7) The DC CMRR specifies the change in the measured differential input voltage value when the common-mode voltage varies:
DC CMRR = –20log(Δ_MAX/FSR) with Δ_MAX being the difference between the minium value and the maximum value measured when sweeping the common-mode voltage.
The DC CMRR is measured with both inputs connected to the common-mode voltage (that is, no differential input signal is applied), and the common-mode voltage is swept from –1 V to V_CC.

(8) The AC CMRR is the difference between a hypothetical signal with the amplitude and frequency of the applied common-mode ripple applied to the inputs of the ADC and the actual common-mode signal spur visible in the FFT spectrum:
AC CMRR = Error Spur [dBFS] – 20log(V_CM / 1.2 V / G) [dBFS] with a common-mode signal of V_CM × sin(2π × f_CM × t) applied to the analog inputs.
The AC CMRR is measured with the both inputs connected to the common-mode signal; that is, no differential input signal is applied.
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).

(9) The AC PSRR is the difference between a hypothetical signal with the amplitude and frequency of the applied supply voltage ripple applied to the inputs of the ADC and the actual supply ripple spur visible in the FFT spectrum:
AC PSRR = Error Spur [dBFS] – 20log(50 mV / 1.2 V / G) [dBFS] with a signal of 50 mV × sin(2π × f_VCC × t) added to V_CC.
The AC PSRR is measured with the inputs grounded; that is, no analog input signal is applied.
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
SD24GAIN: 1 → Hypothetical signal: 20log(50 mV / 1.2 V / 1) = –27.6 dBFS
SD24GAIN: 8 → Hypothetical signal: 20log(50 mV / 1.2 V / 8) = –9.5 dBFS
SD24GAIN: 32 → Hypothetical signal: 20log(50 mV / 1.2 V / 32) = 2.5 dBFS

(10) The crosstalk XT is specified as the tone level of the signal applied to the crosstalk source seen in the spectrum of the converter under test. It is measured with the inputs of the converter under test being grounded.

Table 5-43 lists the AC performance characteristics of the SD24_B.