SLAS396D July   2003  – November 2016 MSP430FE423 , MSP430FE425 , MSP430FE427

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC and DVCC Excluding External Current
    5. 5.5  Thermal Resistance Characteristics, PM Package (LQFP64)
    6. 5.6  Schmitt-Trigger Inputs − Ports (P1 and P2), RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)
    7. 5.7  Inputs P1.x, P2.x, TAx
    8. 5.8  Leakage Current − Ports (P1 and P2)
    9. 5.9  Outputs − Ports (P1 and P2)
    10. 5.10 Output Frequency
    11. 5.11 Typical Characteristics - Ports P1 and P2
    12. 5.12 Wake-up Time From LPM3
    13. 5.13 RAM
    14. 5.14 LCD
    15. 5.15 USART0
    16. 5.16 POR, BOR
    17. 5.17 SVS (Supply Voltage Supervisor and Monitor)
    18. 5.18 DCO
    19. 5.19 Crystal Oscillator, LFXT1 Oscillator
    20. 5.20 ESP430CE1, SD16 and ESP430 Power Supply and Operating Conditions
    21. 5.21 ESP430CE1, SD16 Input Range
    22. 5.22 ESP430CE1, SD16 Performance
    23. 5.23 ESP430CE1, SD16 Temperature Sensor
    24. 5.24 ESP430CE1, SD16 Built-in Voltage Reference
    25. 5.25 ESP430CE1, SD16 Reference Output Buffer
    26. 5.26 ESP430CE1, SD16 External Reference Input
    27. 5.27 ESP430CE1, Active Energy Measurement Test Conditions and Accuracy
    28. 5.28 ESP430CE1, Active Energy Measurement Test Conditions and Accuracy
    29. 5.29 ESP430CE1 Typical Characteristics (I1 SD16GAINx = 1)
    30. 5.30 ESP430CE1 Typical Characteristics (I1 SD16GAINx = 4)
    31. 5.31 ESP430CE1 Typical Characteristics (I1 SD16GAINx = 8)
    32. 5.32 ESP430CE1 Typical Characteristics (I1 SD16GAINx = 32)
    33. 5.33 Flash Memory
    34. 5.34 JTAG Interface
    35. 5.35 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  Oscillator and System Clock
      2. 6.9.2  Brownout, Supply Voltage Supervisor (SVS)
      3. 6.9.3  Digital I/O
      4. 6.9.4  Basic Timer1
      5. 6.9.5  LCD Drive
      6. 6.9.6  Watchdog Timer (WDT+)
      7. 6.9.7  Timer_A3
      8. 6.9.8  USART0
      9. 6.9.9  ESP430CE1
      10. 6.9.10 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      2. 6.10.2 Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
      3. 6.10.3 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger
      4. 6.10.4 Port P2 (P2.2 to P2.5) Input/Output With Schmitt Trigger
      5. 6.10.5 Port P2 (P2.6 and P2.7) Unbonded GPIOs
      6. 6.10.6 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt-Trigger or Output
      7. 6.10.7 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the pinout for the 64-pin PM package.

MSP430FE427 MSP430FE425 MSP430FE423 pinout_pm64.gif

NOTE:

TI recommends leaving all unused analog inputs open.
Figure 4-1 64-Pin PM Package (Top View)

4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants

Table 4-1 Terminal Functions

SIGNAL NAME PIN NO. I/O DESCRIPTION
DVCC 1 Digital supply voltage, positive terminal
I1+ 2 I Current 1 positive analog input, internal connection to SD16 channel 0 A0+(1)
I1− 3 I Current 1 negative analog input, internal connection to SD16 channel 0 A0−(1)
I2+ 4 I Current 2 positive analog input, internal connection to SD16 channel 1 A0+(1)
I2− 5 I Current 2 negative analog input, internal connection to SD16 channel 1 A0−(1)
V1+ 6 I Voltage 1 positive analog input, internal connection to SD16 channel 2 A0+(1)
V1− 7 I Voltage 1 negative analog input, internal connection to SD16 channel 2 A0−(1)
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output terminal of crystal oscillator XT1
VREF 10 I/O Input for an external reference voltage, internal reference voltage output (can be used as mid-voltage)
P2.2/STE0 11 I/O General-purpose digital I/O

Slave transmit enable for USART0 in SPI mode
S0 12 O LCD segment output 0
S1 13 O LCD segment output 1
S2 14 O LCD segment output 2
S3 15 O LCD segment output 3
S4 16 O LCD segment output 4
S5 17 O LCD segment output 5
S6 18 O LCD segment output 6
S7 19 O LCD segment output 7
S8 20 O LCD segment output 8
S9 21 O LCD segment output 9
S10 22 O LCD segment output 10
S11 23 O LCD segment output 11
S12 24 O LCD segment output 12
S13 25 O LCD segment output 13
S14 26 O LCD segment output 14
S15 27 O LCD segment output 15
S16 28 O LCD segment output 16
S17 29 O LCD segment output 17
S18 30 O LCD segment output 18
S19 31 O LCD segment output 19
S20 32 O LCD segment output 20
S21 33 O LCD segment output 21
S22 34 O LCD segment output 22
S23 35 O LCD segment output 23
COM0 36 O Common output, COM0−COM3 are used for LCD backplanes.
COM1 37 O Common output, COM0−COM3 are used for LCD backplanes.
COM2 38 O Common output, COM0−COM3 are used for LCD backplanes.
COM3 39 O Common output, COM0−COM3 are used for LCD backplanes.
R03 40 I Input port of fourth positive (lowest) analog LCD level (V5)
R13 41 I Input port of third most positive analog LCD level (V4 or V3)
R23 42 I Input port of second most positive analog LCD level (V2)
R33 43 O Output port of most positive analog LCD level (V1)
P2.1/UCLK0/S24 44 I/O General-purpose digital I/O

External clock input for USART0 in UART or SPI mode, or
clock output for USART0 in SPI mode

LCD segment output 24(2)

P2.0/TA2/S25 45 I/O General-purpose digital I/O

Timer_A Capture: CCI2A input, Compare: Out2 output

LCD segment output 25(2)

P1.7/SOMI0/S26 46 I/O General-purpose digital I/O

Slave out/master in for USART0 in SPI mode

LCD segment output 26(2)

P1.6/SIMO0/S27 47 I/O General-purpose digital I/O

Slave in/master out for USART0 in SPI mode

LCD segment output 27(2)

P1.5/TACLK/ACLK/S28 48 I/O General-purpose digital I/O

Timer_A and SD16 clock signal TACLK input

ACLK output (divided by 1, 2, 4, or 8)

LCD segment output 28(2)

P1.4/S29 49 I/O General-purpose digital I/O

LCD segment output 29(2)

P1.3/SVSOUT/S30 50 I/O General-purpose digital I/O

SVS: output of SVS comparator

LCD segment output 30(2)

P1.2/TA1/S31 51 I/O General-purpose digital I/O

Timer_A, Capture: CCI1A, CCI1B input, Compare: Out1 output

LCD segment output 31(2)

P1.1/TA0/MCLK 52 I/O General-purpose digital I/O

Timer_A, Capture: CCI0B input. Note: TA0 is only an input on this pin.

MCLK output

BSL receive
P1.0/TA0 53 I/O General-purpose digital I/O

Timer_A, Capture: CCI0A input, Compare: Out0 output

BSL transmit
TDO/TDI 54 I/O Test data output port, TDO/TDI data output or programming data input terminal
TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI.
TMS 56 I Test mode select. TMS is used as an input port for device programming and test.
TCK 57 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 58 I Reset input or nonmaskable interrupt input port
P2.5/URXD0 59 I/O General-purpose digital I/O

Receive data in for USART0 in UART mode
P2.4/UTXD0 60 I/O General-purpose digital I/O

Transmit data out for USART0 in UART mode
P2.3/SVSIN 61 I/O General-purpose digital I/O

Analog input to brownout, supply voltage supervisor
AVSS 62 Analog supply voltage, negative terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive divider circuitry.
DVSS 63 Digital supply voltage, negative terminal
AVCC 64 Analog supply voltage, positive terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive divider circuitry. Do not power up before DVCC.
(1) TI recommends open connection for all unused analog inputs.
(2) LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.