Table 6-1 Instruction Word Formats

Table 6-2 Address Mode Descriptions

Table 6-3 Interrupt Sources, Flags, and Vectors

Table 6-4 Interrupt Enable Register 1 Description

Table 6-5 Interrupt Enable Register 2 Description

Table 6-6 Interrupt Flag Register 1 Description

Table 6-7 Interrupt Flag Register 2 Description

Table 6-8 Module Enable Register 1 Description

Table 6-9 Memory Organization

6.9.1 Oscillator and System Clock

The clock system is supported by the FLL+ module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turnon clock source and stabilizes in less than 6 µs. The FLL+ module provides the following clock signals:

• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
• Main clock (MCLK), the system clock used by the CPU
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8

6.9.2 Brownout, Supply Voltage Supervisor (SVS)

The brownout circuit provides the proper internal reset signal to the device during power on and power off. The SVS circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, V_CC may not have ramped to V_CC(min) at that time. The user must ensure that the default FLL+ settings are not changed until V_CC reaches V_CC(min). If desired, the SVS circuit can be used to determine when V_CC reaches V_CC(min).

6.9.3 Digital I/O

Two I/O ports are implemented: ports P1 and P2 (only six P2 I/O signals are available on external pins).

• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
• Read/write access to port-control registers is supported by all instructions.

6.9.4 Basic Timer1

The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and clock for the LCD module.

6.9.5 LCD Drive

The LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux LCDs are supported by this peripheral.

6.9.6 Watchdog Timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

6.9.7 Timer_A3

Timer_A3 is a 16-bit timer and counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-10). Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

6.9.8 USART0

The MSP430FE42x devices have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3- or 4-pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.

6.9.9 ESP430CE1

The ESP430CE1 module integrates a hardware multiplier, three independent 16-bit Sigma-Delta ADCs (SD16) and an embedded signal processor (ESP430). The ESP430CE1 module measures 2- or 3-wire single-phase energy and automatically calculates parameters which are made available to the MSP430 CPU. The module can be calibrated and initialized to accurately calculate energy, power factor, and other values for a wide range of metering sensor configurations.

6.9.10 Peripheral File Map

Table 6-11 and Table 6-12 list the peripheral registers with their addresses.

6.10.1 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger

Figure 6-8 shows the port diagram. Table 6-13 summarizes the selection of the port function.

NOTE:

0 ≤ x ≤ 1. Port function is active if CAPD.x = 0.

Figure 6-8 Port P1 (P1.0 and P1.1) Diagram

6.10.2 Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger

Figure 6-9 shows the port diagram. Table 6-14 summarizes the selection of the port function.

NOTE:

2 ≤ x ≤ 7. Port function is active if Port/LCD = 0.

Figure 6-9 Port P1 (P1.2 to P1.7) Diagram

Figure 6-10 Direction Control for SIMO0 and SOMI0

6.10.3 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger

Figure 6-11 shows the port diagram. Table 6-15 summarizes the selection of the port function.

NOTE:

0 ≤ x ≤ 1. Port function is active if Port/LCD = 0.

Figure 6-11 Port P2 (P2.0 and P2.1) Diagram

Figure 6-12 Direction Control for UCLK0

6.10.4 Port P2 (P2.2 to P2.5) Input/Output With Schmitt Trigger

Figure 6-13 shows the port diagram. Table 6-16 summarizes the selection of the port function.

NOTE:

2 ≤ x ≤ 5. Port function is active if CAPD.x = 0

Figure 6-13 Port P2 (P2.2 to P2.5) Diagram

6.10.5 Port P2 (P2.6 and P2.7) Unbonded GPIOs

Unbonded GPIOs P2.6 and P2.7 can be used as interrupt flags. Only software can affect the interrupt flags. They work as software interrupts.

Figure 6-14 shows the port diagram. Table 6-17 summarizes the selection of the port function.

NOTE:

x = Bit/identifier, 6 or 7 for Port P2 without external pins

Figure 6-14 Port P2 (P2.6 and P2.7) Diagram

6.10.6 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt-Trigger or Output

Figure 6-15 shows the port diagram.

Figure 6-15 JTAG Pins Diagram

6.10.7 JTAG Fuse Check Mode

MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I_(TF)) of 1.8 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated.

The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see Figure 6-16). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally and therefore do not require external termination.

Figure 6-16 Fuse Check Mode Current