The following table summarizes the
available family members.
Table 6-1 Device Comparison
| Device(1) |
FLASH
(KB)(2) |
SRAM
(KB) |
ADC12 |
DAC12 |
Comp_A |
Timer_A(3) |
Timer_B(4) |
USART |
LCD |
I/Os |
Package Type |
| MSP430FG439 |
60 |
2 |
12 channels |
2 channels |
16 channels |
3 |
3 |
Yes |
Yes |
48 |
80 PN
113
ZCA |
| MSP430FG438 |
48 |
2 |
12 channels |
2 channels |
16 channels |
3 |
3 |
Yes |
Yes |
48 |
80 PN
113
ZCA |
| MSP430FG437 |
32 |
1 |
12 channels |
2 channels |
16 channels |
3 |
3 |
Yes |
Yes |
48 |
80 PN
113
ZCA |
(1) For the most current package and ordering information, see
the Package Option Addendum in
Section 11, or see the TI web site at
www.ti.com.
(2) Package drawings, standard packing quantities, thermal
data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of
Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would
represent two instantiations of Timer_A, the first instantiation having 3
capture/compare registers and PWM output generators and the second
instantiation having 5 capture/compare registers and PWM output generators,
respectively.
(4) Each number in the sequence represents an instantiation of
Timer_B with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would
represent two instantiations of Timer_B, the first instantiation having 3
capture/compare registers and PWM output generators and the second
instantiation having 5 capture/compare registers and PWM output generators,
respectively.