SLAS580E October   2008  – May 2020 MSP430FG477 , MSP430FG478 , MSP430FG479

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC and DVCC Excluding External Current
    5. 5.5  Schmitt-Trigger Inputs – Ports P1 to P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)
    6. 5.6  Inputs Px.y, TAx
    7. 5.7  Leakage Current – Ports P1 to P6
    8. 5.8  Outputs – Ports P1 to P6
    9. 5.9  Output Frequency
    10. 5.10 Typical Characteristics – Outputs
    11. 5.11 Wake-up Timing From LPM3
    12. 5.12 POR – Brownout Reset (BOR)
    13. 5.13 SVS (Supply Voltage Supervisor and Monitor)
    14. 5.14 DCO
    15. 5.15 Crystal Oscillator, LFXT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, LFXT1, High-Frequency Mode
    17. 5.17 Crystal Oscillator, XT2 Oscillator, High-Frequency Mode
    18. 5.18 RAM
    19. 5.19 LCD_A
    20. 5.20 Comparator_A
    21. 5.21 Typical Characteristics – Comparator_A
    22. 5.22 SD16_A, Power Supply and Recommended Operating Conditions
    23. 5.23 SD16_A, Input Range
    24. 5.24 SD16_A, Performance
    25. 5.25 SD16_A, Performance
    26. 5.26 SD16_A, Linearity
    27. 5.27 Typical Characteristics, SD16_A SINAD Performance Over OSR
    28. 5.28 SD16_A, Temperature Sensor and Built-in VCC Sense
    29. 5.29 SD16_A, Built-In Voltage Reference
    30. 5.30 SD16_A, Reference Output Buffer
    31. 5.31 SD16_A, External Reference Input
    32. 5.32 12-Bit DAC, Supply Specifications
    33. 5.33 12-Bit DAC, Linearity Specifications
    34. 5.34 12-Bit DAC, Output Specifications
    35. 5.35 12-Bit DAC, Reference Input Specifications
    36. 5.36 12-Bit DAC, Dynamic Specifications
    37. 5.37 12-Bit DAC, Dynamic Specifications Continued
    38. 5.38 Operational Amplifier OA, Supply Specifications
    39. 5.39 Operational Amplifier OA, Input/Output Specifications
    40. 5.40 Operational Amplifier OA, Dynamic Specifications
    41. 5.41 Operational Amplifier OA, Typical Characteristics
    42. 5.42 Switches Between OA Terminals and Pins
    43. 5.43 OA Typical Characteristics
    44. 5.44 Timer_A
    45. 5.45 Timer_B
    46. 5.46 USCI (UART Mode)
    47. 5.47 USCI (SPI Master Mode)
    48. 5.48 USCI (SPI Slave Mode)
    49. 5.49 USCI (I2C Mode)
    50. 5.50 Flash Memory
    51. 5.51 JTAG Interface
    52. 5.52 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
      1. 6.5.1 Interrupt Enable 1 and 2
      2. 6.5.2 Interrupt Flag Register 1 and 2
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  Oscillator and System Clock
      2. 6.9.2  Brownout, Supply Voltage Supervisor (SVS)
      3. 6.9.3  Digital I/O
      4. 6.9.4  Watchdog Timer (WDT+)
      5. 6.9.5  Basic Timer1 and Real-Time Clock
      6. 6.9.6  LCD_A Drive With Regulated Charge Pump
      7. 6.9.7  Timer_A3
      8. 6.9.8  Timer_B3
      9. 6.9.9  Universal Serial Communication Interface (USCI)
      10. 6.9.10 Comparator_A
      11. 6.9.11 SD16_A
      12. 6.9.12 DAC12
      13. 6.9.13 OA
      14. 6.9.14 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1, P1.1, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P1, P1.2, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P1, P1.3, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P1, P1.4, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P1, P1.5, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P1, P1.6, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P1, P1.7, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P2, P2.0 and P2.1, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P2, P2.2 and P2.3, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P2, P2.4 and P2.5, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P3, P3.0 and P3.3, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P3, P3.1 and P3.2, Input/Output With Schmitt Trigger
      15. 6.10.15 Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      18. 6.10.18 Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger
      19. 6.10.19 Port P6, P6.0 and P6.3, Input/Output With Schmitt Trigger
      20. 6.10.20 Port P6, P6.1 and P6.4, Input/Output With Schmitt Trigger
      21. 6.10.21 Port P6, P6.2, P6.5, and P6.6, Input/Output With Schmitt Trigger
      22. 6.10.22 Port P6, P6.7, Input/Output With Schmitt Trigger
      23. 6.10.23 Segment Pin Schematic: Sx, Dedicated Segment Pins
      24. 6.10.24 Segment Pin Schematic: COM0, Dedicated COM0 Pin
      25. 6.10.25 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
      26. 6.10.26 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Getting Started and Next Steps
      2. 7.1.2 Development Tools Support
        1. 7.1.2.1 Recommended Hardware Options
          1. 7.1.2.1.1 Target Socket Boards
          2. 7.1.2.1.2 Experimenter Boards
          3. 7.1.2.1.3 Debugging and Programming Tools
          4. 7.1.2.1.4 Production Programmers
        2. 7.1.2.2 Recommended Software Options
          1. 7.1.2.2.1 Integrated Development Environments
          2. 7.1.2.2.2 MSP430Ware
          3. 7.1.2.2.3 Command-Line Programmer
      3. 7.1.3 Device Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Related Links
    4. 7.4 Support Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9.14 Peripheral File Map

Table 6-8 lists the registers and addresses for peripherals with word access. Table 6-9 lists the registers and addresses for peripherals with byte access.

Table 6-8 Peripherals With Word Access

MODULE REGISTER NAME ACRONYM ADDRESS
Watchdog Watchdog timer control WDTCTL 0120h
Timer_B3 Capture/compare register 2 TBCCR2 0 96h
Capture/compare register 1 TBCCR1 0 94h
Capture/compare register 0 TBCCR0 0192h
Timer_B register TBR 0190h
Capture/compare control 2 TBCCTL2 0186h
Capture/compare control 1 TBCCTL1 0184h
Capture/compare control 0 TBCCTL0 0182h
Timer_B control TBCTL 0180h
Timer_B interrupt vector TBIV 011Eh
Timer_A3 Capture/compare register 2 TACCR1 0176h
Capture/compare register 1 TACCR1 0174h
Capture/compare register 0 TACCR0 0172h
Timer_A register TAR 0170h
Capture/compare control 2 TACCTL2 0166h
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 0 TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Flash Flash control 4 FCTL4 01BEh
Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
DAC12 DAC12_1 data DAC12_1DAT 01CAh
DAC12_1 control DAC12_1CTL 01C2h
DAC12_0 data DAC12_0DAT 01C8h
DAC12_0 control DAC12_0CTL 01C0h
SD16_A (also see Table 6-9) General control SD16CTL 0100h
Channel 0 control SD16CCTL0 0102h
Channel 0 conversion memory SD16MEM0 0112h
Interrupt vector word register SD16IV 0110h
OA Switches Switch control register 1 SWCTL_1 00CEh

Table 6-9 Peripherals With Byte Access

MODULE REGISTER NAME ACRONYM ADDRESS
OA switches Switch control register
Switch control register 1		 SWCTL
SWCTL1		 0CFh
0CEh
OA1 Operational Amplifier 1 control register 1
Operational Amplifier 1 control register 0		 OA1CTL1
OA1CTL0		 0C3h
0C2h
OA0 Operational Amplifier 0 control register 1
Operational Amplifier 0 control register 0		 OA0CTL1
OA0CTL0		 0C1h
0C0h
SD16_A (also see Table 6-8) Channel 0 input control
Analog enable		 SD16INCTL0
SD16AE		 0B0h
0B7h
LCD_A LCD Voltage Control 1
LCD Voltage Control 0
LCD Voltage Port Control 1
LCD Voltage Port Control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode		 LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDCTL		 0AFh
0AEh
0ADh
0ACh
0A4h
:
0A0h
09Fh
:
091h
090h
USCI_A0, USCI_B0 USCI A0 auto baud rate control
USCI A0 transmit buffer
USCI A0 receive buffer
USCI A0 status
USCI A0 modulation control
USCI A0 baud rate control 1
USCI A0 baud rate control 0
USCI A0 control 1
USCI A0 control 0
USCI A0 IrDA receive control
USCI A0 IrDA transmit control 		UCA0ABCTL
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCTL 		0x005D
0x0067
0x0066
0x0065
0x0064
0x0063
0x0062
0x0061
0x0060
0x005F
0x005E
USCI B0 transmit buffer
USCI B0 receive buffer
USCI B0 status
USCI B0 I2C Interrupt enable
USCI B0 baud rate control 1
USCI B0 baud rate control 0
USCI B0 control 1
USCI B0 control 0
USCI B0 I2C slave address
USCI B0 I2C own address 		UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0CIE
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
UCB0OA 		0x006F
0x006E
0x006D
0x006C
0x006B
0x006A
0x0069
0x0068
0x011A
0x0118
Comparator_A Comparator_A port disable
Comparator_A control 2
Comparator_A control 1		 CAPD
CACTL2
CACTL1		 05Bh
05Ah
059h
Brownout, SVS SVS control register (reset by brownout signal) SVSCTL 056h
FLL+ Clock FLL+ Control 1
FLL+ Control 0
System clock frequency control
System clock frequency integrator
System clock frequency integrator		 FLL_CTL1
FLL_CTL0
SCFQCTL
SCFI1
SCFI0		 054h
053h
052h
051h
050h
RTC
(Basic Timer 1)		 Real Time Clock Year High Byte
Real Time Clock Year Low Byte
Real Time Clock Month
Real Time Clock Day of Month
Basic Timer1 Counter 2
Basic Timer1 Counter 1
Real Time Counter 4 (Real Time Clock Day of Week)
Real Time Counter 3 (Real Time Clock Hour)
Real Time Counter 2 (Real Time Clock Minute)
Real Time Counter 1 (Real Time Clock Second)
Real Time Clock Control
Basic Timer1 Control		 RTCYEARH
RTCYEARL
RTCMON
RTCDAY
BTCNT2
BTCNT1
RTCNT4 (RTCDOW)
RTCNT3 (RTCHOUR)
RTCNT2 (RTCMIN)
RTCNT1 (RTCSEC)
RTCCTL
BTCTL		 04Fh
04Eh
04Dh
04Ch
047h
046h
045h
044h
043h
042h
041h
040h
Port P6 Port P6 selection
Port P6 direction
Port P6 output
Port P6 input		 P6SEL
P6DIR
P6OUT
P6IN		 037h
036h
035h
034h
Port P5 Port P5 selection
Port P5 direction
Port P5 output
Port P5 input		 P5SEL
P5DIR
P5OUT
P5IN		 033h
032h
031h
030h
Port P4 Port P4 selection
Port P4 direction
Port P4 output
Port P4 input		 P4SEL
P4DIR
P4OUT
P4IN		 01Fh
01Eh
01Dh
01Ch
Port P3 Port P3 selection
Port P3 direction
Port P3 output
Port P3 input		 P3SEL
P3DIR
P3OUT
P3IN		 01Bh
01Ah
019h
018h
Port P2 Port P2 selection
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input		 P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN		 02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1 Port P1 selection
Port P1 interrupt enable
Port P1 interrupt-edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input		 P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN		 026h
025h
024h
023h
022h
021h
020h
Special functions SFR module enable 2
SFR module enable 1
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1		 ME2
ME1
IFG2
IFG1
IE2
IE1		 005h
004h
003h
002h
001h
000h