SLAS580E October   2008  – May 2020 MSP430FG477 , MSP430FG478 , MSP430FG479

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC and DVCC Excluding External Current
    5. 5.5  Schmitt-Trigger Inputs – Ports P1 to P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)
    6. 5.6  Inputs Px.y, TAx
    7. 5.7  Leakage Current – Ports P1 to P6
    8. 5.8  Outputs – Ports P1 to P6
    9. 5.9  Output Frequency
    10. 5.10 Typical Characteristics – Outputs
    11. 5.11 Wake-up Timing From LPM3
    12. 5.12 POR – Brownout Reset (BOR)
    13. 5.13 SVS (Supply Voltage Supervisor and Monitor)
    14. 5.14 DCO
    15. 5.15 Crystal Oscillator, LFXT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, LFXT1, High-Frequency Mode
    17. 5.17 Crystal Oscillator, XT2 Oscillator, High-Frequency Mode
    18. 5.18 RAM
    19. 5.19 LCD_A
    20. 5.20 Comparator_A
    21. 5.21 Typical Characteristics – Comparator_A
    22. 5.22 SD16_A, Power Supply and Recommended Operating Conditions
    23. 5.23 SD16_A, Input Range
    24. 5.24 SD16_A, Performance
    25. 5.25 SD16_A, Performance
    26. 5.26 SD16_A, Linearity
    27. 5.27 Typical Characteristics, SD16_A SINAD Performance Over OSR
    28. 5.28 SD16_A, Temperature Sensor and Built-in VCC Sense
    29. 5.29 SD16_A, Built-In Voltage Reference
    30. 5.30 SD16_A, Reference Output Buffer
    31. 5.31 SD16_A, External Reference Input
    32. 5.32 12-Bit DAC, Supply Specifications
    33. 5.33 12-Bit DAC, Linearity Specifications
    34. 5.34 12-Bit DAC, Output Specifications
    35. 5.35 12-Bit DAC, Reference Input Specifications
    36. 5.36 12-Bit DAC, Dynamic Specifications
    37. 5.37 12-Bit DAC, Dynamic Specifications Continued
    38. 5.38 Operational Amplifier OA, Supply Specifications
    39. 5.39 Operational Amplifier OA, Input/Output Specifications
    40. 5.40 Operational Amplifier OA, Dynamic Specifications
    41. 5.41 Operational Amplifier OA, Typical Characteristics
    42. 5.42 Switches Between OA Terminals and Pins
    43. 5.43 OA Typical Characteristics
    44. 5.44 Timer_A
    45. 5.45 Timer_B
    46. 5.46 USCI (UART Mode)
    47. 5.47 USCI (SPI Master Mode)
    48. 5.48 USCI (SPI Slave Mode)
    49. 5.49 USCI (I2C Mode)
    50. 5.50 Flash Memory
    51. 5.51 JTAG Interface
    52. 5.52 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
      1. 6.5.1 Interrupt Enable 1 and 2
      2. 6.5.2 Interrupt Flag Register 1 and 2
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  Oscillator and System Clock
      2. 6.9.2  Brownout, Supply Voltage Supervisor (SVS)
      3. 6.9.3  Digital I/O
      4. 6.9.4  Watchdog Timer (WDT+)
      5. 6.9.5  Basic Timer1 and Real-Time Clock
      6. 6.9.6  LCD_A Drive With Regulated Charge Pump
      7. 6.9.7  Timer_A3
      8. 6.9.8  Timer_B3
      9. 6.9.9  Universal Serial Communication Interface (USCI)
      10. 6.9.10 Comparator_A
      11. 6.9.11 SD16_A
      12. 6.9.12 DAC12
      13. 6.9.13 OA
      14. 6.9.14 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1, P1.1, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P1, P1.2, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P1, P1.3, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P1, P1.4, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P1, P1.5, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P1, P1.6, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P1, P1.7, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P2, P2.0 and P2.1, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P2, P2.2 and P2.3, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P2, P2.4 and P2.5, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P3, P3.0 and P3.3, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P3, P3.1 and P3.2, Input/Output With Schmitt Trigger
      15. 6.10.15 Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      18. 6.10.18 Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger
      19. 6.10.19 Port P6, P6.0 and P6.3, Input/Output With Schmitt Trigger
      20. 6.10.20 Port P6, P6.1 and P6.4, Input/Output With Schmitt Trigger
      21. 6.10.21 Port P6, P6.2, P6.5, and P6.6, Input/Output With Schmitt Trigger
      22. 6.10.22 Port P6, P6.7, Input/Output With Schmitt Trigger
      23. 6.10.23 Segment Pin Schematic: Sx, Dedicated Segment Pins
      24. 6.10.24 Segment Pin Schematic: COM0, Dedicated COM0 Pin
      25. 6.10.25 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
      26. 6.10.26 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Getting Started and Next Steps
      2. 7.1.2 Development Tools Support
        1. 7.1.2.1 Recommended Hardware Options
          1. 7.1.2.1.1 Target Socket Boards
          2. 7.1.2.1.2 Experimenter Boards
          3. 7.1.2.1.3 Debugging and Programming Tools
          4. 7.1.2.1.4 Production Programmers
        2. 7.1.2.2 Recommended Software Options
          1. 7.1.2.2.1 Integrated Development Environments
          2. 7.1.2.2.2 MSP430Ware
          3. 7.1.2.2.3 Command-Line Programmer
      3. 7.1.3 Device Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Related Links
    4. 7.4 Support Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.2 Signal Descriptions

Table 4-1 describes the device signals.

Table 4-1 Signal Descriptions

SIGNAL NAME PIN NO. I/O DESCRIPTION
PN ZCA, ZQW
AVCC 52 F12 Analog supply voltage, positive terminal.
AVSS 53 E12 Analog supply voltage, negative terminal.
DVCC1 1 A1 Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS1 79 A3 Digital supply voltage, negative terminal. Supplies all digital parts.
DVCC2 80 A2 Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS2 78 B2, B3 Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TA0/OA0RFB 58 C11 I/O General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
Range switch to OA0 output
BSL transmit
P1.1/TA0/MCLK/OA1RFB 57 C12 I/O General-purpose digital I/O pin
Timer_A, capture: CCI0B input, compare: Out0 output
MCLK signal output
Range switch to OA1 output
BSL receive
P1.2/TA1/A4-/OA0I3 (SW0C) 56 D11 I/O General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
SD16 negative analog input A4
OA0, analog input I3
P1.3/TBOUTH/SVSOUT/A4+/ OA1I3 (SW1C) 55 D12 I/O General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: Out2 output
Set all PWM digital output ports to high impedance - Timer_B TB0 to TB2
SVS comparator output
SD16 positive analog input A4
OA1, analog input I3
P1.4/TBCLK/SMCLK/A3-/ OA1I0/DAC1 54 E11 I/O General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
SMCLK signal output
SD16 negative analog input A3
OA1, analog input I0
DAC12.1 output
P1.5/TACLK/ ACLK/A3+ 51 F11 I/O General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ACLK signal output
SD16 positive analog input A3
P1.6/CA0/A2- / OA0I0/DAC0 50 G12 I/O General-purpose digital I/O pin
Comparator_A input 0
SD16 negative analog input A2
OA0, analog input I0
DAC12.0 output
P1.7/CA1/A2+ 49 G11 I/O General-purpose digital I/O pin
Comparator_A input 1
SD16 positive analog input A2
P2.0/TA2/S1 4 C2, C3 I/O General-purpose digital I/O pin
Timer_A, capture: CCI2A/B input, compare: Out2 output
LCD segment output 1
P2.1/TB0/S0 3 C1 I/O General-purpose digital I/O pin
Timer_B, capture: CCI0A/B input, compare: Out0 output
LCD segment output 0
P2.2/TB1 2 B1 I/O General-purpose digital I/O pin
Timer_B, capture: CCI1A/B input, compare: Out1 output
P2.3/TB2 77 B4 I/O General-purpose digital I/O pin
Timer_B, capture: CCI2A/B input, compare: Out2 output
P2.4/UCA0TXD/ UCA0SIMO 76 A4 I/O General-purpose digital I/O pin
USCIA transmit data output in UART mode, slave data in/master out in SPI mode
P2.5/UCA0RXD/ UCA0SOMI 75 D4 I/O General-purpose digital I/O pin
USCI A0 receive data input in UART mode, slave data out/master in in SPI mode
P2.6/CAOUT/S2 5 D1 I/O General-purpose digital I/O pin
Comparator_A output
LCD segment output 2
P2.7/S3 6 D2 I/O General-purpose digital I/O pin
LCD segment output 3
P3.0/UCB0STE/ UCA0CLK 41 M12 I/O General-purpose digital I/O pin
USCI B0 slave transmit enable
USCI A0 clock input/output
P3.1/UCB0SIMO/ UCB0SDA/S26 42 L12 I/O General-purpose digital I/O pin
USCI B0 slave in/master out in SPI mode, SDA I2C data in I2C mode
LCD segment output 26
P3.2/UCB0SOMI/ UCB0SCL/S27 43 K11 I/O General-purpose digital I/O pin
USCI B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode
LCD segment output 27
P3.3/UCB0CLK/ UCA0STE 44 K12 I/O General-purpose digital I/O
USCI B0 clock input/output, USCI A0 slave transmit enable
P3.4/S28 45 J11 I/O General-purpose digital I/O pin
LCD segment output 28
P3.5/S29 46 J12 I/O General-purpose digital I/O pin
LCD segment output 29
P3.6/S30 47 H11 I/O General-purpose digital I/O pin
LCD segment output 30
P3.7/S31 48 H12 I/O General-purpose digital I/O pin
LCD segment output 31
P4.0/S11 18 K2 I/O General-purpose digital I/O pin
LCD segment output 11
P4.1/S10 17 K1 I/O General-purpose digital I/O pin
LCD segment output 10
P4.2/S9 16 J2 I/O General-purpose digital I/O pin
LCD segment output 9
P4.3/S8 15 J1 I/O General-purpose digital I/O pin
LCD segment output 8
P4.4/S7 14 H2 I/O General-purpose digital I/O pin
LCD segment output 7
P4.5/S6 13 H1 I/O General-purpose digital I/O pin
LCD segment output 6
P4.6/S5 12 G2 I/O General-purpose digital I/O pin
LCD segment output 5
P4.7/S4 11 G1 I/O General-purpose digital I/O pin
LCD segment output 4
COM0 33 L8 O Common output, COM0- 3 are used for LCD backplanes
P5.0/S20 27 L5 I/O General-purpose digital I/O pin
LCD segment output 20
P5.1/S21 28 M5 I/O General-purpose digital I/O pin
LCD segment output 21
P5.2/COM1 34 M8 I/O General-purpose digital I/O pin
common output, COM0- 3 are used for LCD backplanes
P5.3/COM2 35 L9 I/O General-purpose digital I/O pin
common output, COM0- 3 are used for LCD backplanes
P5.4/COM3 36 M9 I/O General-purpose digital I/O pin
common output, COM0- 3 are used for LCD backplanes
LCDCAP/R33 37 J9 I/O Capacitor connection for LCD charge pump
input port of most positive analog LCD level (V4)
P5.5/R23 38 M10 I/O General-purpose digital I/O pin
input port of the second most positive analog LCD level (V3)
P5.6/LCDREF/ R13 39 L10 I/O General-purpose digital I/O pin
External LCD reference voltage input
input port of the third most positive analog LCD level (V3 or V2)
P5.7/R03 40 M11 I/O General-purpose digital I/O pin
input port of the fourth most positive analog LCD level (V1)
P6.0/A0+/OA0O 67 B8 I/O General-purpose digital I/O pin
SD16 positive analog input A0
OA0, output
P6.1/A0- /OA0FB 66 B9 I/O General-purpose digital I/O pin
SD16 positive negative input A0
OA0, analog input feedback
P6.2/OA0I1 (SW0A) 65 A9 I/O General-purpose digital I/O pin
OA0, analog input I1
P6.3/A1+/OA1O 64 D9 I/O General-purpose digital I/O pin
SD16 positive analog input A1
OA1, output
P6.4/A1- /OA1FB 63 A10 I/O General-purpose digital I/O pin
SD16 positive negative input A1
OA1, analog input feedback
P6.5/OA0I2 (SW0B) 62 B10 I/O General-purpose digital I/O pin
OA0, analog input I2
P6.6/OA1I1 (SW1A) 61 A11 I/O General-purpose digital I/O pin
OA1, analog input I1
P6.7/OA1I2/ SVSIN (SW1B) 59 B12 I/O General-purpose digital I/O pin
OA1, analog input I2
SVS input
S12 19 L1 O LCD segment output 12
S13 20 M1 O LCD segment output 13
S14 21 M2 O LCD segment output 14
S15 22 M3 O LCD segment output 15
S16 23 L3 O LCD segment output 16
S17 24 L4 O LCD segment output 17
S18 25 M4 O LCD segment output 18
S19 26 J4 O LCD segment output 19
S22 29 L6 O LCD segment output 22
S23 30 M6 O LCD segment output 23
S24 31 L7 O LCD segment output 24
S25 32 M7 O LCD segment output 25
GND 7 E2 Ground. It is used to shield the oscillator. See Note 1.
XIN 8 E1 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 F1 O Output port for crystal oscillator XT1. Standard or watch crystals can be connected.
GND 10 F2 Ground. It is used to shield the oscillator.(1)
VREF 60 A12 O Input for an external reference voltage/internal reference voltage output
RST/NMI 74 B5 I Reset input, nonmaskable interrupt input port, or bootloader start (in flash devices).
TCK 73 A5 I Test clock (JTAG). TCK is the clock input port for device programming test and bootloader start.
TDI/TCLK 71 A6 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI 70 B7 I/O Test data output port. TDO/TDI data output or programming data input terminal.
TMS 72 B6 I Test mode select. TMS is used as an input port for device programming and test.
XT2OUT 68 A8 O Output terminal of crystal oscillator XT2
XT2IN 69 A7 I Input port for crystal oscillator XT2
Reserved NA B11, D6, D7, D8, E4, E5, E6, E7, E8, E9, F4, F5, F8, F9, G4, G5,G8, G9, H4, H5, H6, H7, H8, H9, J5, J6, J7, J8, L2, L11 Unused BGA balls. Connection to DVSS/AVSS recommended.
(1) It is recommended to connect GND externally to DVSS.