SLAS580E October   2008  – May 2020 MSP430FG477 , MSP430FG478 , MSP430FG479

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC and DVCC Excluding External Current
    5. 5.5  Schmitt-Trigger Inputs – Ports P1 to P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)
    6. 5.6  Inputs Px.y, TAx
    7. 5.7  Leakage Current – Ports P1 to P6
    8. 5.8  Outputs – Ports P1 to P6
    9. 5.9  Output Frequency
    10. 5.10 Typical Characteristics – Outputs
    11. 5.11 Wake-up Timing From LPM3
    12. 5.12 POR – Brownout Reset (BOR)
    13. 5.13 SVS (Supply Voltage Supervisor and Monitor)
    14. 5.14 DCO
    15. 5.15 Crystal Oscillator, LFXT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, LFXT1, High-Frequency Mode
    17. 5.17 Crystal Oscillator, XT2 Oscillator, High-Frequency Mode
    18. 5.18 RAM
    19. 5.19 LCD_A
    20. 5.20 Comparator_A
    21. 5.21 Typical Characteristics – Comparator_A
    22. 5.22 SD16_A, Power Supply and Recommended Operating Conditions
    23. 5.23 SD16_A, Input Range
    24. 5.24 SD16_A, Performance
    25. 5.25 SD16_A, Performance
    26. 5.26 SD16_A, Linearity
    27. 5.27 Typical Characteristics, SD16_A SINAD Performance Over OSR
    28. 5.28 SD16_A, Temperature Sensor and Built-in VCC Sense
    29. 5.29 SD16_A, Built-In Voltage Reference
    30. 5.30 SD16_A, Reference Output Buffer
    31. 5.31 SD16_A, External Reference Input
    32. 5.32 12-Bit DAC, Supply Specifications
    33. 5.33 12-Bit DAC, Linearity Specifications
    34. 5.34 12-Bit DAC, Output Specifications
    35. 5.35 12-Bit DAC, Reference Input Specifications
    36. 5.36 12-Bit DAC, Dynamic Specifications
    37. 5.37 12-Bit DAC, Dynamic Specifications Continued
    38. 5.38 Operational Amplifier OA, Supply Specifications
    39. 5.39 Operational Amplifier OA, Input/Output Specifications
    40. 5.40 Operational Amplifier OA, Dynamic Specifications
    41. 5.41 Operational Amplifier OA, Typical Characteristics
    42. 5.42 Switches Between OA Terminals and Pins
    43. 5.43 OA Typical Characteristics
    44. 5.44 Timer_A
    45. 5.45 Timer_B
    46. 5.46 USCI (UART Mode)
    47. 5.47 USCI (SPI Master Mode)
    48. 5.48 USCI (SPI Slave Mode)
    49. 5.49 USCI (I2C Mode)
    50. 5.50 Flash Memory
    51. 5.51 JTAG Interface
    52. 5.52 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
      1. 6.5.1 Interrupt Enable 1 and 2
      2. 6.5.2 Interrupt Flag Register 1 and 2
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  Oscillator and System Clock
      2. 6.9.2  Brownout, Supply Voltage Supervisor (SVS)
      3. 6.9.3  Digital I/O
      4. 6.9.4  Watchdog Timer (WDT+)
      5. 6.9.5  Basic Timer1 and Real-Time Clock
      6. 6.9.6  LCD_A Drive With Regulated Charge Pump
      7. 6.9.7  Timer_A3
      8. 6.9.8  Timer_B3
      9. 6.9.9  Universal Serial Communication Interface (USCI)
      10. 6.9.10 Comparator_A
      11. 6.9.11 SD16_A
      12. 6.9.12 DAC12
      13. 6.9.13 OA
      14. 6.9.14 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1, P1.1, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P1, P1.2, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P1, P1.3, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P1, P1.4, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P1, P1.5, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P1, P1.6, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P1, P1.7, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P2, P2.0 and P2.1, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P2, P2.2 and P2.3, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P2, P2.4 and P2.5, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P3, P3.0 and P3.3, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P3, P3.1 and P3.2, Input/Output With Schmitt Trigger
      15. 6.10.15 Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      18. 6.10.18 Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger
      19. 6.10.19 Port P6, P6.0 and P6.3, Input/Output With Schmitt Trigger
      20. 6.10.20 Port P6, P6.1 and P6.4, Input/Output With Schmitt Trigger
      21. 6.10.21 Port P6, P6.2, P6.5, and P6.6, Input/Output With Schmitt Trigger
      22. 6.10.22 Port P6, P6.7, Input/Output With Schmitt Trigger
      23. 6.10.23 Segment Pin Schematic: Sx, Dedicated Segment Pins
      24. 6.10.24 Segment Pin Schematic: COM0, Dedicated COM0 Pin
      25. 6.10.25 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
      26. 6.10.26 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Getting Started and Next Steps
      2. 7.1.2 Development Tools Support
        1. 7.1.2.1 Recommended Hardware Options
          1. 7.1.2.1.1 Target Socket Boards
          2. 7.1.2.1.2 Experimenter Boards
          3. 7.1.2.1.3 Debugging and Programming Tools
          4. 7.1.2.1.4 Production Programmers
        2. 7.1.2.2 Recommended Software Options
          1. 7.1.2.2.1 Integrated Development Environments
          2. 7.1.2.2.2 MSP430Ware
          3. 7.1.2.2.3 Command-Line Programmer
      3. 7.1.3 Device Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Related Links
    4. 7.4 Support Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, flash is not programmed) the CPU goes into LPM4 immediately after power-up.

Table 6-3 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
PC Out-of-Range(4) 		PORIFG
RSTIFG
WDTIFG
KEYV (1) 		Reset 0FFFEh 15, highest
NMI
Oscillator Fault
Flash Memory Access Violation		 NMIIFG (1)(3)
OFIFG(1)(3)
ACCVIFG(1)(2) 		(Non)maskable
(Non)maskable
(Non)maskable		 0FFFCh 14
Timer_B3 TBCCR0 CCIFG0(2) Maskable 0FFFAh 13
Timer_B3 TBCCR1 CCIFG1 and TBCCR2 CCIFG2, TBIFG(1)(2) Maskable 0FFF8h 12
Comparator_A CAIFG Maskable 0FFF6h 11
Watchdog Timer+ WDTIFG Maskable 0FFF4h 10
USCI_A0, USCI_B0 Receive,
USCI_B0 I2C status		 UCA0RXIFG, UCB0RXIFG(1)(5) Maskable 0FFF2h 9
USCI_A0, USCI_B0 Transmit,
USCI_B0 I2C receive/transmit		 UCA0TXIFG, UCB0TXIFG (1)(6) Maskable 0FFF0h 8
SD16_A SD16CCTLx SD16OVIFG, SD16CCTLx SD16IFG (1)(2) Maskable 0FFEEh 7
Timer_A3 TACCR0 CCIFG0(2) Maskable 0FFECh 6
Timer_A3 TACCR1 CCIFG1 and TACCR2 CCIFG2, TAIFG(1)(2) Maskable 0FFEAh 5
I/O Port P1 (8 Flags) P1IFG.0 to P1IFG.7(1)(2) Maskable 0FFE8h 4
DAC12 DAC12_0IFG, DAC12_1IFG Maskable 0FFE6h 3
Maskable 0FFE4h 2
I/O Port P2 (8 Flags) P2IFG.0 to P2IFG.7 (1)(2) Maskable 0FFE2h 1
Basic Timer 1, RTC BTIFG Maskable 0FFE0h 0, lowest
(1) Multiple source flags
(2) Interrupt flags are located in the module.
(3) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Access and key violations, KEYV and ACCVIFG.
(5) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
(6) In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.