SLASE58E
February 2016 – December 2019
MSP430FR2310
,
MSP430FR2311
PRODUCTION DATA.
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Device Comparison
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Pin Diagrams
4.2
Pin Attributes
4.3
Signal Descriptions
4.4
Pin Multiplexing
4.5
Buffer Type
4.6
Connection of Unused Pins
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Active Mode Supply Current Into VCC Excluding External Current
5.5
Active Mode Supply Current Per MHz
5.6
Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
5.7
Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
5.8
Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
5.9
Production Distribution of LPM Supply Currents
5.10
Typical Characteristics – Current Consumption Per Module
5.11
Thermal Resistance Characteristics
5.12
Timing and Switching Characteristics
5.12.1
Power Supply Sequencing
Table 5-1
PMM, SVS and BOR
5.12.2
Reset Timing
Table 5-2
Wake-up Times From Low-Power Modes and Reset
5.12.3
Clock Specifications
Table 5-3
XT1 Crystal Oscillator (Low Frequency)
Table 5-4
XT1 Crystal Oscillator (High Frequency)
Table 5-5
DCO FLL
Table 5-6
DCO Frequency
Table 5-7
REFO
Table 5-8
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
Table 5-9
Module Oscillator (MODOSC)
5.12.4
Digital I/Os
Table 5-10
Digital Inputs
Table 5-11
Digital Outputs
5.12.4.1
Digital I/O Typical Characteristics
5.12.5
VREF+ Built-in Reference
Table 5-12
VREF+
5.12.6
Timer_B
Table 5-13
Timer_B
5.12.7
eUSCI
Table 5-14
eUSCI (UART Mode) Clock Frequency
Table 5-15
eUSCI (UART Mode) Switching Characteristics
Table 5-16
eUSCI (SPI Master Mode) Clock Frequency
Table 5-17
eUSCI (SPI Master Mode) Switching Characteristics
Table 5-18
eUSCI (SPI Slave Mode) Switching Characteristics
Table 5-19
eUSCI (I2C Mode) Switching Characteristics
5.12.8
ADC
Table 5-20
ADC, Power Supply and Input Range Conditions
Table 5-21
ADC, 10-Bit Timing Parameters
Table 5-22
ADC, 10-Bit Linearity Parameters
5.12.9
Enhanced Comparator (eCOMP)
Table 5-23
eCOMP0
5.12.10
Smart Analog Combo (SAC)
Table 5-24
SAC0 (SAC-L1, OA)
5.12.11
Transimpedance Amplifier (TIA)
Table 5-25
TIA0
5.12.12
FRAM
Table 5-26
FRAM
5.12.13
Emulation and Debug
Table 5-27
JTAG, Spy-Bi-Wire Interface
Table 5-28
JTAG, 4-Wire Interface
6
Detailed Description
6.1
Overview
6.2
CPU
6.3
Operating Modes
6.4
Interrupt Vector Addresses
6.5
Memory Organization
6.6
Bootloader (BSL)
6.7
JTAG Standard Interface
6.8
Spy-Bi-Wire Interface (SBW)
6.9
FRAM
6.10
Memory Protection
6.11
Peripherals
6.11.1
Power-Management Module (PMM) and On-chip Reference Voltages
6.11.2
Clock System (CS) and Clock Distribution
6.11.3
General-Purpose Input/Output Port (I/O)
6.11.4
Watchdog Timer (WDT)
6.11.5
System Module (SYS)
6.11.6
Cyclic Redundancy Check (CRC)
6.11.7
Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
6.11.8
Timers (Timer0_B3, Timer1_B3)
6.11.9
Backup Memory (BAKMEM)
6.11.10
Real-Time Clock (RTC) Counter
6.11.11
10-Bit Analog-to-Digital Converter (ADC)
6.11.12
eCOMP0
6.11.13
SAC0
6.11.14
TIA0
6.11.15
eCOMP0, SAC0, TIA0, and ADC in SOC Interconnection
6.11.16
Embedded Emulation Module (EEM)
6.11.17
Peripheral File Map
6.12
Input/Output Diagrams
6.12.1
Port P1 Input/Output With Schmitt Trigger
6.12.2
Port P2 Input/Output With Schmitt Trigger
6.13
Device Descriptors (TLV)
6.14
Identification
6.14.1
Revision Identification
6.14.2
Device Identification
6.14.3
JTAG Identification
7
Applications, Implementation, and Layout
7.1
Device Connection and Layout Fundamentals
7.1.1
Power Supply Decoupling and Bulk Capacitors
7.1.2
External Oscillator
7.1.3
JTAG
7.1.4
Reset
7.1.5
Unused Pins
7.1.6
General Layout Recommendations
7.1.7
Do's and Don'ts
7.2
Peripheral- and Interface-Specific Design Information
7.2.1
ADC Peripheral
7.2.1.1
Partial Schematic
7.2.1.2
Design Requirements
7.2.1.3
Layout Guidelines
7.3
Typical Applications
8
Device and Documentation Support
8.1
Getting Started
8.2
Device Nomenclature
8.3
Tools and Software
8.4
Documentation Support
8.5
Related Links
8.6
Community Resources
8.7
Trademarks
8.8
Electrostatic Discharge Caution
8.9
Glossary
9
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PW|20
MPDS362A
PW|16
MPDS361A
RGY|16
MPQF115G
Thermal pad, mechanical data (Package|Pins)
RGY|16
QFND040P
Orderable Information
slase58e_oa
slase58e_pm
Table 5-13
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN
MAX
UNIT
f
TB
Timer_B input clock frequency
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
2.0 V, 3.0 V
16
MHz
t
TB,cap
Timer_B capture timing
All capture inputs, minimum pulse duration required for capture
2.0 V, 3.0 V
20
ns