SLASE58E February 2016 – December 2019 MSP430FR2310 , MSP430FR2311
PRODUCTION DATA.
The Timer0_B3 and Timer1_B3 modules are 16-bit timers and counters with three capture/compare registers each. Each can support multiple captures or compares, PWM outputs, and interval timing (see Table 6-13 and Table 6-14). Each has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. The CCR0 registers on TB0 and TB1 are not externally connected and can be used only for hardware period timing and interrupt generation. In Up mode, they can set the overflow value of the counter.
The interconnection of Timer0_B3 and Timer1_B3 can modulate the eUSCI_A pin of UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated infrared command for directly driving an external IR diode (see Figure 6-2). The IR functions are fully controlled by the SYS configuration registers including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSSEL (data select), and IRDATA (data) bits. For more information, see the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.
PORT PIN | DEVICE INPUT SIGNAL | MODULE INPUT NAME | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL |
---|---|---|---|---|---|
P2.7 | TB0CLK | TBCLK | Timer | N/A | |
ACLK (internal) | ACLK | ||||
SMCLK (internal) | SMCLK | ||||
From Capacitive Touch I/O (internal) | INCLK | ||||
From RTC (internal) | CCI0A | CCR0 | TB0 | ||
ACLK (internal) | CCI0B | Timer1_B3 CCI0B input | |||
DVSS | GND | ||||
DVCC | VCC | ||||
P1.6 | TB0.1 | CCI1A | CCR1 | TB1 | TB0.1 |
From eCOMP (internal) | CCI1B | Timer1_B3 CCI1B input | |||
DVSS | GND | ||||
DVCC | VCC | ||||
P1.7 | TB0.2 | CCI2A | CCR2 | TB2 | TB0.2 |
From Capacitive Touch I/O (internal) | CCI2B | Timer1_B3 INCLK
Timer1_B3 CCI2B input, IR input |
|||
DVSS | GND | ||||
DVCC | VCC |
PORT PIN | DEVICE INPUT SIGNAL | MODULE INPUT NAME | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL |
---|---|---|---|---|---|
P2.2 | TB1CLK | TBCLK | Timer | N/A | |
ACLK (internal) | ACLK | ||||
SMCLK (internal) | SMCLK | ||||
Timer0_B3 CCR2B output (internal) | INCLK | ||||
DVSS | CCI0A | CCR0 | TB0 | ||
Timer0_B3 CCR0B output (internal) | CCI0B | ||||
DVSS | GND | ||||
DVCC | VCC | ||||
P2.0 | TB1.1 | CCI1A | CCR1 | TB1 | TB1.1 |
Timer0_B3 CCR1B output (internal) | CCI1B | To ADC trigger | |||
DVSS | GND | ||||
DVCC | VCC | ||||
P2.1 | TB1.2 | CCI2A | CCR2 | TB2 | TB1.2 |
Timer0_B3 CCR2B output (internal) | CCI2B | IR input | |||
DVSS | GND | ||||
DVCC | VCC |
The Timer_B module includes a feature that puts all Timer_B outputs into a high-impedance state when the selected source is triggered. The source can be selected from an external pin or an internal signal, and it is controlled by TBxTRG in SYS. For more information, see the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.
Table 6-15 lists the Timer_B high-impedance trigger source selections.
TBxTRGSEL | TBxOUTH TRIGGER SOURCE SELECTION | Timer_B PAD OUTPUT HIGH IMPEDANCE |
---|---|---|
TB0TRGSEL = 0 | eCOMP0 output (internal) | P1.6, P1.7 |
TB0TRGSEL= 1 | P1.2 | |
TB1TRGSEL = 0 | eCOMP0 output (internal) | P2.0, P2.1 |
TB1TRGSEL = 1 | P2.3 |