SLASE59F October 2015 – December 2019 MSP430FR2433
PRODUCTION DATA.
Table 6-24 lists the available peripherals and the register base address for each. Table 6-25 to Table 6-44 list the registers and address offsets for each peripheral.
MODULE NAME | BASE ADDRESS | SIZE |
---|---|---|
Special Functions (See Table 6-25) | 0100h | 0010h |
PMM (See Table 6-26) | 0120h | 0020h |
SYS (See Table 6-27) | 0140h | 0040h |
CS (See Table 6-28) | 0180h | 0020h |
FRAM (See Table 6-29) | 01A0h | 0010h |
CRC (See Table 6-30) | 01C0h | 0008h |
WDT (See Table 6-31) | 01CCh | 0002h |
Port P1, P2 (See Table 6-32) | 0200h | 0020h |
Port P3 (See Table 6-33) | 0220h | 0020h |
RTC (See Table 6-34) | 0300h | 0010h |
Timer0_A3 (See Table 6-35) | 0380h | 0030h |
Timer1_A3 (See Table 6-36) | 03C0h | 0030h |
Timer2_A2 (See Table 6-37) | 0400h | 0030h |
Timer3_A2 (See Table 6-38) | 0440h | 0030h |
MPY32 (See Table 6-39) | 04C0h | 0030h |
eUSCI_A0 (See Table 6-40) | 0500h | 0020h |
eUSCI_A1 (See Table 6-41) | 0520h | 0020h |
eUSCI_B0 (See Table 6-42) | 0540h | 0030h |
Backup Memory (See Table 6-43) | 0660h | 0020h |
ADC (See Table 6-44) | 0700h | 0040h |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
SFR interrupt enable | SFRIE1 | 00h |
SFR interrupt flag | SFRIFG1 | 02h |
SFR reset pin control | SFRRPCR | 04h |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
PMM control 0 | PMMCTL0 | 00h |
PMM control 1 | PMMCTL1 | 02h |
PMM control 2 | PMMCTL2 | 04h |
PMM interrupt flags | PMMIFG | 0Ah |
PM5 control 0 | PM5CTL0 | 10h |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
System control | SYSCTL | 00h |
Bootloader configuration area | SYSBSLC | 02h |
JTAG mailbox control | SYSJMBC | 06h |
JTAG mailbox input 0 | SYSJMBI0 | 08h |
JTAG mailbox input 1 | SYSJMBI1 | 0Ah |
JTAG mailbox output 0 | SYSJMBO0 | 0Ch |
JTAG mailbox output 1 | SYSJMBO1 | 0Eh |
Bus error vector generator | SYSBERRIV | 18h |
User NMI vector generator | SYSUNIV | 1Ah |
System NMI vector generator | SYSSNIV | 1Ch |
Reset vector generator | SYSRSTIV | 1Eh |
System configuration 0 | SYSCFG0 | 20h |
System configuration 1 | SYSCFG1 | 22h |
System configuration 2 | SYSCFG2 | 24h |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
CS control 0 | CSCTL0 | 00h |
CS control 1 | CSCTL1 | 02h |
CS control 2 | CSCTL2 | 04h |
CS control 3 | CSCTL3 | 06h |
CS control 4 | CSCTL4 | 08h |
CS control 5 | CSCTL5 | 0Ah |
CS control 6 | CSCTL6 | 0Ch |
CS control 7 | CSCTL7 | 0Eh |
CS control 8 | CSCTL8 | 10h |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
FRAM control 0 | FRCTL0 | 00h |
General control 0 | GCCTL0 | 04h |
General control 1 | GCCTL1 | 06h |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
CRC data input | CRC16DI | 00h |
CRC data input reverse byte | CRCDIRB | 02h |
CRC initialization and result | CRCINIRES | 04h |
CRC result reverse byte | CRCRESR | 06h |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
Watchdog timer control | WDTCTL | 00h |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
RTC control | RTCCTL | 00h |
RTC interrupt vector | RTCIV | 04h |
RTC modulo | RTCMOD | 08h |
RTC counter | RTCCNT | 0Ch |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
TA0 control | TA0CTL | 00h |
Capture/compare control 0 | TA0CCTL0 | 02h |
Capture/compare control 1 | TA0CCTL1 | 04h |
Capture/compare control 2 | TA0CCTL2 | 06h |
TA0 counter | TA0R | 10h |
Capture/compare 0 | TA0CCR0 | 12h |
Capture/compare 1 | TA0CCR1 | 14h |
Capture/compare 2 | TA0CCR2 | 16h |
TA0 expansion 0 | TA0EX0 | 20h |
TA0 interrupt vector | TA0IV | 2Eh |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
TA1 control | TA1CTL | 00h |
Capture/compare control 0 | TA1CCTL0 | 02h |
Capture/compare control 1 | TA1CCTL1 | 04h |
Capture/compare control 2 | TA1CCTL2 | 06h |
TA1 counter | TA1R | 10h |
Capture/compare 0 | TA1CCR0 | 12h |
Capture/compare 1 | TA1CCR1 | 14h |
Capture/compare 2 | TA1CCR2 | 16h |
TA1 expansion 0 | TA1EX0 | 20h |
TA1 interrupt vector | TA1IV | 2Eh |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
TA2 control | TA2CTL | 00h |
Capture/compare control 0 | TA2CCTL0 | 02h |
Capture/compare control 1 | TA2CCTL1 | 04h |
TA2 counter | TA2R | 10h |
Capture/compare 0 | TA2CCR0 | 12h |
Capture/compare 1 | TA2CCR1 | 14h |
TA2 expansion 0 | TA2EX0 | 20h |
TA2 interrupt vector | TA2IV | 2Eh |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
TA3 control | TA3CTL | 00h |
Capture/compare control 0 | TA3CCTL0 | 02h |
Capture/compare control 1 | TA3CCTL1 | 04h |
TA3 counter | TA3R | 10h |
Capture/compare 0 | TA3CCR0 | 12h |
Capture/compare 1 | TA3CCR1 | 14h |
TA3 expansion 0 | TA3EX0 | 20h |
TA3 interrupt vector | TA3IV | 2Eh |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
16-bit operand 1 – multiply | MPY | 00h |
16-bit operand 1 – signed multiply | MPYS | 02h |
16-bit operand 1 – multiply accumulate | MAC | 04h |
16-bit operand 1 – signed multiply accumulate | MACS | 06h |
16-bit operand 2 | OP2 | 08h |
16 × 16 result low word | RESLO | 0Ah |
16 × 16 result high word | RESHI | 0Ch |
16 × 16 sum extension | SUMEXT | 0Eh |
32-bit operand 1 – multiply low word | MPY32L | 10h |
32-bit operand 1 – multiply high word | MPY32H | 12h |
32-bit operand 1 – signed multiply low word | MPYS32L | 14h |
32-bit operand 1 – signed multiply high word | MPYS32H | 16h |
32-bit operand 1 – multiply accumulate low word | MAC32L | 18h |
32-bit operand 1 – multiply accumulate high word | MAC32H | 1Ah |
32-bit operand 1 – signed multiply accumulate low word | MACS32L | 1Ch |
32-bit operand 1 – signed multiply accumulate high word | MACS32H | 1Eh |
32-bit operand 2 – low word | OP2L | 20h |
32-bit operand 2 – high word | OP2H | 22h |
32 × 32 result 0 – least significant word | RES0 | 24h |
32 × 32 result 1 | RES1 | 26h |
32 × 32 result 2 | RES2 | 28h |
32 × 32 result 3 – most significant word | RES3 | 2Ah |
MPY32 control 0 | MPY32CTL0 | 2Ch |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
eUSCI_A control word 0 | UCA0CTLW0 | 00h |
eUSCI_A control word 1 | UCA0CTLW1 | 02h |
eUSCI_A control rate 0 | UCA0BR0 | 06h |
eUSCI_A control rate 1 | UCA0BR1 | 07h |
eUSCI_A modulation control | UCA0MCTLW | 08h |
eUSCI_A status | UCA0STAT | 0Ah |
eUSCI_A receive buffer | UCA0RXBUF | 0Ch |
eUSCI_A transmit buffer | UCA0TXBUF | 0Eh |
eUSCI_A LIN control | UCA0ABCTL | 10h |
eUSCI_A IrDA transmit control | lUCA0IRTCTL | 12h |
eUSCI_A IrDA receive control | IUCA0IRRCTL | 13h |
eUSCI_A interrupt enable | UCA0IE | 1Ah |
eUSCI_A interrupt flags | UCA0IFG | 1Ch |
eUSCI_A interrupt vector word | UCA0IV | 1Eh |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
eUSCI_A control word 0 | UCA1CTLW0 | 00h |
eUSCI_A control word 1 | UCA1CTLW1 | 02h |
eUSCI_A control rate 0 | UCA1BR0 | 06h |
eUSCI_A control rate 1 | UCA1BR1 | 07h |
eUSCI_A modulation control | UCA1MCTLW | 08h |
eUSCI_A status | UCA1STAT | 0Ah |
eUSCI_A receive buffer | UCA1RXBUF | 0Ch |
eUSCI_A transmit buffer | UCA1TXBUF | 0Eh |
eUSCI_A LIN control | UCA1ABCTL | 10h |
eUSCI_A IrDA transmit control | lUCA1IRTCTL | 12h |
eUSCI_A IrDA receive control | IUCA1IRRCTL | 13h |
eUSCI_A interrupt enable | UCA1IE | 1Ah |
eUSCI_A interrupt flags | UCA1IFG | 1Ch |
eUSCI_A interrupt vector word | UCA1IV | 1Eh |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
eUSCI_B control word 0 | UCB0CTLW0 | 00h |
eUSCI_B control word 1 | UCB0CTLW1 | 02h |
eUSCI_B bit rate 0 | UCB0BR0 | 06h |
eUSCI_B bit rate 1 | UCB0BR1 | 07h |
eUSCI_B status word | UCB0STATW | 08h |
eUSCI_B byte counter threshold | UCB0TBCNT | 0Ah |
eUSCI_B receive buffer | UCB0RXBUF | 0Ch |
eUSCI_B transmit buffer | UCB0TXBUF | 0Eh |
eUSCI_B I2C own address 0 | UCB0I2COA0 | 14h |
eUSCI_B I2C own address 1 | UCB0I2COA1 | 16h |
eUSCI_B I2C own address 2 | UCB0I2COA2 | 18h |
eUSCI_B I2C own address 3 | UCB0I2COA3 | 1Ah |
eUSCI_B receive address | UCB0ADDRX | 1Ch |
eUSCI_B address mask | UCB0ADDMASK | 1Eh |
eUSCI_B I2C slave address | UCB0I2CSA | 20h |
eUSCI_B interrupt enable | UCB0IE | 2Ah |
eUSCI_B interrupt flags | UCB0IFG | 2Ch |
eUSCI_B interrupt vector word | UCB0IV | 2Eh |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
Backup memory 0 | BAKMEM0 | 00h |
Backup memory 1 | BAKMEM1 | 02h |
Backup memory 2 | BAKMEM2 | 04h |
Backup memory 3 | BAKMEM3 | 06h |
Backup memory 4 | BAKMEM4 | 08h |
Backup memory 5 | BAKMEM5 | 0Ah |
Backup memory 6 | BAKMEM6 | 0Ch |
Backup memory 7 | BAKMEM7 | 0Eh |
Backup memory 8 | BAKMEM8 | 10h |
Backup memory 9 | BAKMEM9 | 12h |
Backup memory 10 | BAKMEM10 | 14h |
Backup memory 11 | BAKMEM11 | 16h |
Backup memory 12 | BAKMEM12 | 18h |
Backup memory 13 | BAKMEM13 | 1Ah |
Backup memory 14 | BAKMEM14 | 1Ch |
Backup memory 15 | BAKMEM15 | 1Eh |
REGISTER DESCRIPTION | ACRONYM | OFFSET |
---|---|---|
ADC control 0 | ADCCTL0 | 00h |
ADC control 1 | ADCCTL1 | 02h |
ADC control 2 | ADCCTL2 | 04h |
ADC window comparator low threshold | ADCLO | 06h |
ADC window comparator high threshold | ADCHI | 08h |
ADC memory control 0 | ADCMCTL0 | 0Ah |
ADC conversion memory | ADCMEM0 | 12h |
ADC interrupt enable | ADCIE | 1Ah |
ADC interrupt flags | ADCIFG | 1Ch |
ADC interrupt vector word | ADCIV | 1Eh |