SLASEO5D March   2019  – September 2021 MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Types
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics – Low-Power Mode Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Resistance Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 DCO Frequency
        4. 8.12.3.4 REFO
        5. 8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. 8.12.3.6 Module Oscillator (MODOSC)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Typical Characteristics – Outputs at 3 V and 2 V
      5. 8.12.5  Internal Shared Reference
        1. 8.12.5.1 Internal Reference Characteristics
      6. 8.12.6  Timer_A and Timer_B
        1. 8.12.6.1 Timer_A
        2. 8.12.6.2 Timer_B
      7. 8.12.7  eUSCI
        1. 8.12.7.1 eUSCI (UART Mode) Clock Frequency
        2. 8.12.7.2 eUSCI (UART Mode) Timing Characteristics
        3. 8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.12.7.4 eUSCI (SPI Master Mode)
        5. 8.12.7.5 eUSCI (SPI Slave Mode)
        6. 8.12.7.6 eUSCI (I2C Mode)
      8. 8.12.8  ADC
        1. 8.12.8.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.8.2 ADC, Timing Parameters
        3. 8.12.8.3 ADC, Linearity Parameters
      9. 8.12.9  Enhanced Comparator (eCOMP)
        1. 8.12.9.1 eCOMP0 Characteristics
      10. 8.12.10 CapTIvate
        1. 8.12.10.1 CapTIvate Electrical Characteristics
        2. 8.12.10.2 CapTIvate Signal-to-Noise Ratio Characteristics
      11. 8.12.11 FRAM
        1. 8.12.11.1 FRAM Characteristics
      12. 8.12.12 Debug and Emulation
        1. 8.12.12.1 JTAG, 4-Wire and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Bootloader (BSL)
    6. 9.6  JTAG Standard Interface
    7. 9.7  Spy-Bi-Wire Interface (SBW)
    8. 9.8  FRAM
    9. 9.9  Memory Protection
    10. 9.10 Peripherals
      1. 9.10.1  Power-Management Module (PMM)
      2. 9.10.2  Clock System (CS) and Clock Distribution
      3. 9.10.3  General-Purpose Input/Output Port (I/O)
      4. 9.10.4  Watchdog Timer (WDT)
      5. 9.10.5  System (SYS) Module
      6. 9.10.6  Cyclic Redundancy Check (CRC)
      7. 9.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 9.10.8  Timers (TA0, TA1, TA2, TA3 and TB0)
      9. 9.10.9  Hardware Multiplier (MPY)
      10. 9.10.10 Backup Memory (BAKMEM)
      11. 9.10.11 Real-Time Clock (RTC)
      12. 9.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 9.10.13 eCOMP0
      14. 9.10.14 CapTIvate Technology
      15. 9.10.15 Embedded Emulation Module (EEM)
    11. 9.11 Input/Output Diagrams
      1. 9.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.11.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.11.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.11.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.11.5 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      6. 9.11.6 Port P6 (P6.0 to P6.2) Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptors
    13. 9.13 Memory
      1. 9.13.1 Memory Organization
      2. 9.13.2 Peripheral File Map
    14. 9.14 Identification
      1. 9.14.1 Revision Identification
      2. 9.14.2 Device Identification
      3. 9.14.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
      2. 10.2.2 CapTIvate Peripheral
        1. 10.2.2.1 Device Connection and Layout Fundamentals
        2. 10.2.2.2 125
        3. 10.2.2.3 Measurements
          1. 10.2.2.3.1 SNR
          2. 10.2.2.3.2 Sensitivity
          3. 10.2.2.3.3 Power
    3. 10.3 CapTIvate Technology Evaluation
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.12.5.1 Internal Reference Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VSENSOR Temperature sensor voltage TJ = 30℃ 2.0 V, 3.0 V 788 mV
TCSENSOR Temperature sensor coefficient TJ = 30℃ 2.5 mV/°C
VeCOMP, LP Low-power threshold for eCOMP TJ = 30℃ 2.0 V, 3.0 V 1.20 V
VREF+, 1.2V Output Positive built-in reference output at VREF+ pin with 1-mA load current to ground EXTREFEN = 1 with 1-mA load current 2.0 V, 3.0 V 1.16 1.20 1.24 V
TCREF+, 1.2V Temperature coefficient of VREF+ = 1.2 V built-in reference EXTREFEN = 1 with 1-mA load current 3.0 V 30 µV/°C
The following parameters are for the 1.5-V, 2.0-V, and 2.5-V internal reference only and cannot be output to the VREF+ pin.
VREF+, 1.5V, 2.0V, 2.5V Positive built-in reference voltage as internal reference REFVSEL = {2} for 2.5 V,
INTREFEN = 1		 3.0 V 2.5 ±1.5% V
REFVSEL = {1} for 2.0 V,
INTREFEN = 1		 2.5 V 2.0 ±1.5%
REFVSEL = {0} for 1.5 V,
INTREFEN = 1		 2.0 V 1.5 ±1.8%
Noise RMS noise at VREF (3) From 0.1 Hz to 10 Hz,
REFVSEL = {0}		 30 130 µV
DVCC(min) DVCC minimum voltage, Positive built-in reference active REFVSEL = {0} for 1.5 V 1.8 V
REFVSEL = {1} for 2.0 V 2.2
REFVSEL = {2} for 2.5 V 2.7
IREF+ Operating supply current into DVCC terminal(1) INTREFEN = 1 3 V 19 26 µA
IREF+_ADC_BUF Operating supply current into AVCC terminal(1) ADC ON, REFVSEL = {0, 1, 2} 3 V 247 400 µA
IO(VREF+) VREF (1.5 V, 2.0 V, 2.5 V) maximum load current, VREF+ terminal REFVSEL = {0, 1, 2},
AVCC = AVCC(min) for each reference level, INTREFEN = 1		 3 V -1000 +10 µA
ΔVout/ ΔIo (VREF+) Load-current regulation, VREF+ terminal REFVSEL = {0, 1, 2},
IO(VREF+) = +10 µA or -1000 µA
AVCC = AVCC(min) for each reference level, INTREFEN = 1		 3 V 1500 µV/mA
CVREF+/- Capacitance at VREF+ and VREF- terminals INTREFEN = 1 3 V 0 100 pF
TCREF+ Temperature coefficient of built-in reference REFVSEL = {0, 1, 2},
INTREFEN = 1,
TA = –40°C to 105°C(4)		 3 V 24 50 ppm/K
PSRR_DC Power supply rejection ratio (DC) AVCC = AVCC(min) to AVCC(max), TA = 25°C, REFVSEL = {0, 1, 2},
INTREFEN = 1		 3 V 100 420 µV/V
PSRR_AC Power supply rejection ratio (AC) ΔAVCC= 0.1 V at 1 kHz 3 V 3.0 mV/V
tSETTLE Settling time of reference voltage(2) AVCC = AVCC(min) to AVCC(max),
REFVSEL = {0, 1, 2},
INTREFEN = 0 → 1		 3 V 75 100 µs
(1) The internal reference current is supplied through the AVCC terminal.
(2) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
(3) The internal reference noise affects ADC performance when the ADC uses the internal reference.
(4) Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))