SLASEO5D March   2019  – September 2021 MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Types
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics – Low-Power Mode Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Resistance Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 DCO Frequency
        4. 8.12.3.4 REFO
        5. 8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. 8.12.3.6 Module Oscillator (MODOSC)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Typical Characteristics – Outputs at 3 V and 2 V
      5. 8.12.5  Internal Shared Reference
        1. 8.12.5.1 Internal Reference Characteristics
      6. 8.12.6  Timer_A and Timer_B
        1. 8.12.6.1 Timer_A
        2. 8.12.6.2 Timer_B
      7. 8.12.7  eUSCI
        1. 8.12.7.1 eUSCI (UART Mode) Clock Frequency
        2. 8.12.7.2 eUSCI (UART Mode) Timing Characteristics
        3. 8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.12.7.4 eUSCI (SPI Master Mode)
        5. 8.12.7.5 eUSCI (SPI Slave Mode)
        6. 8.12.7.6 eUSCI (I2C Mode)
      8. 8.12.8  ADC
        1. 8.12.8.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.8.2 ADC, Timing Parameters
        3. 8.12.8.3 ADC, Linearity Parameters
      9. 8.12.9  Enhanced Comparator (eCOMP)
        1. 8.12.9.1 eCOMP0 Characteristics
      10. 8.12.10 CapTIvate
        1. 8.12.10.1 CapTIvate Electrical Characteristics
        2. 8.12.10.2 CapTIvate Signal-to-Noise Ratio Characteristics
      11. 8.12.11 FRAM
        1. 8.12.11.1 FRAM Characteristics
      12. 8.12.12 Debug and Emulation
        1. 8.12.12.1 JTAG, 4-Wire and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Bootloader (BSL)
    6. 9.6  JTAG Standard Interface
    7. 9.7  Spy-Bi-Wire Interface (SBW)
    8. 9.8  FRAM
    9. 9.9  Memory Protection
    10. 9.10 Peripherals
      1. 9.10.1  Power-Management Module (PMM)
      2. 9.10.2  Clock System (CS) and Clock Distribution
      3. 9.10.3  General-Purpose Input/Output Port (I/O)
      4. 9.10.4  Watchdog Timer (WDT)
      5. 9.10.5  System (SYS) Module
      6. 9.10.6  Cyclic Redundancy Check (CRC)
      7. 9.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 9.10.8  Timers (TA0, TA1, TA2, TA3 and TB0)
      9. 9.10.9  Hardware Multiplier (MPY)
      10. 9.10.10 Backup Memory (BAKMEM)
      11. 9.10.11 Real-Time Clock (RTC)
      12. 9.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 9.10.13 eCOMP0
      14. 9.10.14 CapTIvate Technology
      15. 9.10.15 Embedded Emulation Module (EEM)
    11. 9.11 Input/Output Diagrams
      1. 9.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.11.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.11.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.11.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.11.5 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      6. 9.11.6 Port P6 (P6.0 to P6.2) Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptors
    13. 9.13 Memory
      1. 9.13.1 Memory Organization
      2. 9.13.2 Peripheral File Map
    14. 9.14 Identification
      1. 9.14.1 Revision Identification
      2. 9.14.2 Device Identification
      3. 9.14.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
      2. 10.2.2 CapTIvate Peripheral
        1. 10.2.2.1 Device Connection and Layout Fundamentals
        2. 10.2.2.2 125
        3. 10.2.2.3 Measurements
          1. 10.2.2.3.1 SNR
          2. 10.2.2.3.2 Sensitivity
          3. 10.2.2.3.3 Power
    3. 10.3 CapTIvate Technology Evaluation
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 9-2). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 9-2 Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCEINTERRUPT FLAGSYSTEM INTERRUPTWORD ADDRESSPRIORITY
System Reset
Power up, Brownout, Supply supervisor
External reset RST
Watchdog time-out, key violation
FRAM uncorrectable bit error detection
Software POR, BOR
FLL unlock error		 
SVSHIFG
PMMRSTIFG
WDTIFG
PMMPORIFG, PMMBORIFG
SYSRSTIV
FLLUNLOCKIFG		ResetFFFEh63, Highest
System NMI
Vacant memory access
JTAG mailbox
FRAM access time error
FRAM bit error detection		VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG		NonmaskableFFFCh62
User NMI
External NMI
Oscillator fault		NMIIFG
OFIFG		NonmaskableFFFAh61
Timer0_A3TA0CCR0 CCIFG0MaskableFFF8h60
Timer0_A3TA0CCR1 CCIFG1, TA0CCR2 CCIFG2, TA0IFG (TA0IV)MaskableFFF6h59
Timer1_A3TA1CCR0 CCIFG0MaskableFFF4h58
Timer1_A3TA1CCR1 CCIFG1, TA1CCR2 CCIFG2, TA1IFG (TA1IV)MaskableFFF2h57
Time2_A3TA2CCR0 CCIFG0MaskableFFF0h56
Timer2_A3TA2CCR1 CCIFG1, TA2CCR2 CCIFG2, TA2IFG (TA2IV)MaskableFFEEh55
Timer3_A3TA3CCR0 CCIFG0MaskableFFECh54
Timer3_A3TA3CCR1 CCIFG1, TA3CCR2 CCIFG2, TA3IFG (TA3IV)MaskableFFEAh53
Timer0_B7TB0CCR0 CCIFG0MaskableFFE8h52
Timer0_B7TB0CCR1 CCIFG1, TB0CCR2 CCIFG2, TB0CCR3 CCIFG3, TB0CCR4 CCIFG4, TB0CCR5 CCIFG5, TB0CCR6 CCIFG6, TB0IFG (TB0IV)MaskableFFE6h51
RTCRTCIFGMaskableFFE4h50
Watchdog timer interval modeWDTIFGMaskableFFE2h49
eUSCI_A0 receive or transmitUCTXCPTIFG, UCSTTIFG, UCRXIFG, UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV)		MaskableFFE0h48
eUSCI_A1 receive or transmitUCTXCPTIFG, UCSTTIFG, UCRXIFG, UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV)		MaskableFFDEh47
eUSCI_B0 receive or transmitUCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV)		MaskableFFDCh46
eUSCI_B1 receive or transmitUCB1RXIFG, UCB1TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV)		MaskableFFDAh45
ADCADCIFG0, ADCINIFG, ADCLOIFG, ADCHIIFG, ADCTOVIFG, ADCOVIFG (ADCIV)MaskableFFD8h44
P1P1IFG.0 to P1IFG.7 (P1IV)MaskableFFD6h43
P2P2IFG.0 to P2IFG.7 (P2IV)MaskableFFD4h42
P3P3IFG.0 to P2IFG.7 (P3IV)MaskableFFD2h41
P4P4IFG.0 to P4IFG.7 (P4IV)MaskableFFD0h40
P5P5IFG.0 to P5IFG.7 (P5IV)MaskableFFCEh39
P6P6IFG.0 to P6IFG.2 (P6IV)MaskableFFCCh38
eCOMP0CPIIFG, CPIFG (CP0IV)MaskableFFCAh37
CapTIvate(see CapTivate Design Center for details) MaskableFFC8h36, Lowest
ReservedReservedMaskableFFC6h–FF88h
Table 9-3 Signatures
SIGNATUREWORD ADDRESS
BSL I2C Address(1)0FFA0h
BSL Config0FF8Ah
BSL Config Signature0FF88h
BSL Signature20FF86h
BSL Signature10FF84h
JTAG Signature20FF82h
JTAG Signature10FF80h
(1) 7-bit address BSL I2C interface