SLASEF5 Data sheet

SLASEF5B January 2019 – December 2021 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

PM|64
- MTQF008B
RGC|64
- MPQF125F

Thermal pad, mechanical data (Package|Pins)

Orderable Information

9.14.1 Port Function Select Registers (PySEL1 , PySEL0)

Port pins are multiplexed with peripheral module functions as described in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide. The functions of each port pin are controlled by its port function select registers, PySEL1 and PySEL0, where y = port number. The bits in the registers are mapped to the pins in the port. The primary module function, secondary module function, and tertiary module function of the pins are determined by the configuration of the PySEL1.x bit and the PySEL0.x bit as shown in Table 9-24. For example, P1SEL1.0 and P1SEL0.0 determine the primary module function, secondary module function, and tertiary module function of the P1.0 pin, which is in port 1. The module functions may also require the PxDIR bits to be configured according to the direction needed for the module function.

Table 9-24 I/O Function Selection

I/O FUNCTIONS	PySEL1.x⁽¹⁾	PySEL0.x⁽¹⁾
General purpose I/O is selected	0	0
Primary module function is selected	0	1
Secondary module function is selected	1	0
Tertiary module function is selected	1	1

(1) y = port, x = bit

See the port pin function tables in the following sections for the configurations of the function and direction for each pin.