SLASE35C May 2014 – December 2017 MSP430FR5720 , MSP430FR5721 , MSP430FR5722 , MSP430FR5723 , MSP430FR5724 , MSP430FR5725 , MSP430FR5726 , MSP430FR5727 , MSP430FR5728 , MSP430FR5729
PRODUCTION DATA.
CAUTION | These products use FRAM nonvolatile memory technology. FRAM retention is sensitive to extreme temperatures, such as those experienced during reflow or hand soldering. See Absolute Maximum Ratings for more information. |
CAUTION | System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturb of data or code memory. See MSP430™ System-Level ESD Considerations for more information. |
The TI MSP430FR572x family of ultra-low-power microcontrollers consists of multiple devices that feature embedded FRAM nonvolatile memory, ultra-low-power 16-bit MSP430™ CPU, and different peripherals targeted for various applications. The architecture, FRAM, and peripherals, combined with seven low-power modes, are optimized to achieve extended battery life in portable and wireless sensing applications. FRAM is a new nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and reliability of flash, all at lower total power consumption. Peripherals include a 10-bit ADC, a 16-channel comparator with voltage reference generation and hysteresis capabilities, three enhanced serial channels capable of I2C, SPI, or UART protocols, an internal DMA, a hardware multiplier, an RTC, five 16-bit timers, and digital I/Os.
PART NUMBER | PACKAGE | BODY SIZE(2) |
---|---|---|
MSP430FR5729RHA | VQFN (40) | 6 mm × 6 mm |
MSP430FR5729DA | TSSOP (38) | 12.5 mm × 6.2 mm |
MSP430FR5728RGE | VQFN (24) | 4 mm × 4 mm |
MSP430FR5728PW | TSSOP (28) | 9.7 mm × 4.4 mm |
Figure 1-1 shows the functional block diagram for the MSP430FR5721, MSP430FR5725, and MSP430FR5729 devices in the RHA package. For the functional block diagrams for all device variants and package options, see Section 6.1.
Changes from October 1, 2016 to December 5, 2017
Table 3-1 summarizes the available family members.
DEVICE | FRAM (KB) |
SRAM (KB) |
SYSTEM CLOCK (MHz) |
ADC10_B | Comp_D | Timer_A(1) | Timer_B(2) | eUSCI | I/O | PACKAGE | |
---|---|---|---|---|---|---|---|---|---|---|---|
Channel A: UART, IrDA, SPI |
Channel B: SPI, I2C |
||||||||||
MSP430FR5729 | 16 | 1 | 8 | 12 ext, 2 int ch. | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5728 | 16 | 1 | 8 | 6 ext, 2 int ch. | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
8 ext, 2 int ch. | 12 ch. | 21 | PW | ||||||||
MSP430FR5727 | 16 | 1 | 8 | – | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5726 | 16 | 1 | 8 | – | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
12 ch. | 21 | PW | |||||||||
MSP430FR5725 | 8 | 1 | 8 | 12 ext, 2 int ch. | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5724 | 8 | 1 | 8 | 6 ext, 2 int ch. | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
8 ext, 2 int ch. | 12 ch. | 21 | PW | ||||||||
MSP430FR5723 | 8 | 1 | 8 | – | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5722 | 8 | 1 | 8 | – | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
12 ch. | 21 | PW | |||||||||
MSP430FR5721 | 4 | 1 | 8 | 12 ext, 2 int ch. | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5720 | 4 | 1 | 8 | 6 ext, 2 int ch. | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
8 ext, 2 int ch. | 12 ch. | 21 | PW |
For information about other devices in this family of products or related products, see the following links.
Figure 4-1 shows the pin diagram for the MSP430FR5721, MSP430FR5723, MSP430FR5725, MSP430FR5727, and MSP430FR5729 devices in the 40-pin RHA package.
NOTE:
Exposed thermal pad connection to VSS recommended.Figure 4-2 shows the pin diagram for the MSP430FR5721, MSP430FR5723, MSP430FR5725, MSP430FR5727, and MSP430FR5729 devices in the 38-pin DA package.
Figure 4-3 shows the pin diagram for the MSP430FR5720, MSP430FR5722, MSP430FR5724, MSP430FR5726, and MSP430FR5728 devices in the 24-pin RGE package.
NOTE:
Exposed thermal pad connection to VSS recommended.Figure 4-4 shows the pin diagram for the MSP430FR5720, MSP430FR5722, MSP430FR5724, MSP430FR5726, and MSP430FR5728 devices in the 28-pin PW package.
Table 4-1 describes the signals for all device variants and packages.
TERMINAL | I/O (1) | DESCRIPTION | ||||
---|---|---|---|---|---|---|
NAME | NO. | |||||
RHA | RGE | DA | PW | |||
P1.0/TA0.1/DMAE0/ RTCCLK/A0/CD0/VeREF- | 1 | 1 | 5 | 5 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TA0 CCR1 capture: CCI1A input, compare: Out1 | ||||||
External DMA trigger | ||||||
RTC clock calibration output | ||||||
Analog input A0 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD0 | ||||||
External applied reference voltage (not available on devices without ADC) | ||||||
P1.1/TA0.2/TA1CLK/ CDOUT/A1/CD1/VeREF+ | 2 | 2 | 6 | 6 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TA0 CCR2 capture: CCI2A input, compare: Out2 | ||||||
TA1 input clock | ||||||
Comparator_D output | ||||||
Analog input A1 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD1 | ||||||
Input for an external reference voltage to the ADC (not available on devices without ADC) | ||||||
P1.2/TA1.1/TA0CLK/ CDOUT/A2/CD2 | 3 | 3 | 7 | 7 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TA1 CCR1 capture: CCI1A input, compare: Out1 | ||||||
TA0 input clock | ||||||
Comparator_D output | ||||||
Analog input A2 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD2 | ||||||
P3.0/A12/CD12 | 4 | N/A | 8 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
Analog input A12 – ADC (not available on devices without ADC or package options PW, RGE) | ||||||
Comparator_D input CD12 (not available on package options PW, RGE) | ||||||
P3.1/A13/CD13 | 5 | N/A | 9 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
Analog input A13 – ADC (not available on devices without ADC or package options PW, RGE) | ||||||
Comparator_D input CD13 (not available on package options PW, RGE) | ||||||
P3.2/A14/CD14 | 6 | N/A | 10 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
Analog input A14 – ADC (not available on devices without ADC or package options PW, RGE) | ||||||
Comparator_D input CD14 (not available on package options PW, RGE) | ||||||
P3.3/A15/CD15 | 7 | N/A | 11 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
Analog input A15 – ADC (not available on devices without ADC or package options PW, RGE) | ||||||
Comparator_D input CD15 (not available on package options PW, RGE) | ||||||
P1.3/TA1.2/UCB0STE/ A3/CD3 | 8 | 4 | 12 | 8 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TA1 CCR2 capture: CCI2A input, compare: Out2 | ||||||
Slave transmit enable – eUSCI_B0 SPI mode | ||||||
Analog input A3 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD3 | ||||||
P1.4/TB0.1/UCA0STE/ A4/CD4 | 9 | 5 | 13 | 9 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB0 CCR1 capture: CCI1A input, compare: Out1 | ||||||
Slave transmit enable – eUSCI_A0 SPI mode | ||||||
Analog input A4 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD4 | ||||||
P1.5/TB0.2/UCA0CLK/ A5/CD5 | 10 | 6 | 14 | 10 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB0 CCR2 capture: CCI2A input, compare: Out2 | ||||||
Clock signal input – eUSCI_A0 SPI slave mode, Clock signal output – eUSCI_A0 SPI master mode |
||||||
Analog input A5 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD5 | ||||||
PJ.0/TDO/TB0OUTH/ SMCLK/CD6 (4) | 11 | 7 | 15 | 11 | I/O | General-purpose digital I/O |
Test data output port | ||||||
Switch all PWM outputs high impedance input – TB0 | ||||||
SMCLK output | ||||||
Comparator_D input CD6 | ||||||
PJ.1/TDI/TCLK/TB1OUTH/ MCLK/CD7 (4) | 12 | 8 | 16 | 12 | I/O | General-purpose digital I/O |
Test data input or test clock input | ||||||
Switch all PWM outputs high impedance input – TB1 (not available on devices without TB1) | ||||||
MCLK output | ||||||
Comparator_D input CD7 | ||||||
PJ.2/TMS/TB2OUTH/ ACLK/CD8 (4) | 13 | 9 | 17 | 13 | I/O | General-purpose digital I/O |
Test mode select | ||||||
Switch all PWM outputs high impedance input – TB2 (not available on devices without TB2) | ||||||
ACLK output | ||||||
Comparator_D input CD8 | ||||||
PJ.3/TCK/CD9 (4) | 14 | 10 | 18 | 14 | I/O | General-purpose digital I/O |
Test clock | ||||||
Comparator_D input CD9 | ||||||
P4.0/TB2.0 | 15 | N/A | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
TB2 CCR0 capture: CCI0B input, compare: Out0 (not available on devices without TB2 or package options DA, PW, RGE) | ||||||
P4.1 | 16 | N/A | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options DA, PW, RGE) |
P2.5/TB0.0/UCA1TXD/ UCA1SIMO | 17 | N/A | 19 | 15 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB0 CCR0 capture: CCI0A input, compare: Out0 | ||||||
Transmit data – eUSCI_A1 UART mode, Slave in, master out – eUSCI_A1 SPI mode (not available on devices without UCSI_A1) | ||||||
P2.6/TB1.0/UCA1RXD/ UCA1SOMI | 18 | N/A | 20 | 16 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB1) | ||||||
Receive data – eUSCI_A1 UART mode, Slave out, master in – eUSCI_A1 SPI mode (not available on devices without UCSI_A1) | ||||||
TEST/SBWTCK (4) (3) | 19 | 11 | 21 | 17 | I | Test mode pin – enable JTAG pins |
Spy-Bi-Wire input clock | ||||||
RST/NMI/SBWTDIO (4) (3) | 20 | 12 | 22 | 18 | I/O | Reset input active low |
Non-maskable interrupt input | ||||||
Spy-Bi-Wire data input/output | ||||||
P2.0/TB2.0/UCA0TXD/ UCA0SIMO/TB0CLK/ACLK (3) | 21 | 13 | 23 | 19 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB2 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB2) | ||||||
Transmit data – eUSCI_A0 UART mode | ||||||
Slave in, master out – eUSCI_A0 SPI mode | ||||||
TB0 clock input | ||||||
ACLK output | ||||||
P2.1/TB2.1/UCA0RXD/ UCA0SOMI/TB0.0 (3) | 22 | 14 | 24 | 20 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB2 CCR1 capture: CCI1A input, compare: Out1 (not available on devices without TB2) | ||||||
Receive data – eUSCI_A0 UART mode | ||||||
Slave out, master in – eUSCI_A0 SPI mode | ||||||
TB0 CCR0 capture: CCI0A input, compare: Out0 | ||||||
P2.2/TB2.2/UCB0CLK/ TB1.0 | 23 | 15 | 25 | 21 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB2 CCR2 capture: CCI2A input, compare: Out2 (not available on devices without TB2) | ||||||
Clock signal input – eUSCI_B0 SPI slave mode, Clock signal output – eUSCI_B0 SPI master mode |
||||||
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB1) | ||||||
P3.4/TB1.1/TB2CLK/ SMCLK | 24 | N/A | 26 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
TB1 CCR1 capture: CCI1B input, compare: Out1 (not available on devices without TB1) | ||||||
TB2 clock input (not available on devices without TB2 or package options PW, RGE) | ||||||
SMCLK output (not available on package options PW, RGE) | ||||||
P3.5/TB1.2/CDOUT | 25 | N/A | 27 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
TB1 CCR2 capture: CCI2B input, compare: Out2 (not available on devices without TB1) | ||||||
Comparator_D output (not available on package options PW, RGE) | ||||||
P3.6/TB2.1/TB1CLK | 26 | N/A | 28 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
TB2 CCR1 capture: CCI1B input, compare: Out1 (not available on devices without TB2) | ||||||
TB1 clock input (not available on devices without TB1 or package options PW, RGE) | ||||||
P3.7/TB2.2 | 27 | N/A | 29 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
TB2 CCR2 capture: CCI2B input, compare: Out2 (not available on devices without TB2 or package options PW, RGE) | ||||||
P1.6/TB1.1/UCB0SIMO/ UCB0SDA/TA0.0 | 28 | 16 | 30 | 22 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB1 CCR1 capture: CCI1A input, compare: Out1 (not available on devices without TB1) | ||||||
Slave in, master out – eUSCI_B0 SPI mode | ||||||
I2C data – eUSCI_B0 I2C mode | ||||||
TA0 CCR0 capture: CCI0A input, compare: Out0 | ||||||
P1.7/TB1.2/UCB0SOMI/ UCB0SCL/TA1.0 | 29 | 17 | 31 | 23 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB1 CCR2 capture: CCI2A input, compare: Out2 (not available on devices without TB1) | ||||||
Slave out, master in – eUSCI_B0 SPI mode | ||||||
I2C clock – eUSCI_B0 I2C mode | ||||||
TA1 CCR0 capture: CCI0A input, compare: Out0 | ||||||
VCORE (2) | 30 | 18 | 32 | 24 | Regulated core power supply (internal use only, no external current loading) | |
DVSS | 31 | 19 | 33 | 25 | Digital ground supply | |
DVCC | 32 | 20 | 34 | 26 | Digital power supply | |
P2.7 | 33 | N/A | 35 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
P2.3/TA0.0/UCA1STE/ A6/CD10 | 34 | N/A | 36 | 27 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options RGE) |
TA0 CCR0 capture: CCI0B input, compare: Out0 (not available on package options RGE) | ||||||
Slave transmit enable – eUSCI_A1 SPI mode (not available on devices without eUSCI_A1) | ||||||
Analog input A6 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD10 (not available on package options RGE) | ||||||
P2.4/TA1.0/UCA1CLK/ A7/CD11 | 35 | N/A | 37 | 28 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options RGE) |
TA1 CCR0 capture: CCI0B input, compare: Out0 (not available on package options RGE) | ||||||
Clock signal input – eUSCI_A1 SPI slave mode, Clock signal output – eUSCI_A1 SPI master mode (not available on devices without eUSCI_A1) | ||||||
Analog input A7 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD11 (not available on package options RGE) | ||||||
AVSS | 36 | N/A | 38 | N/A | Analog ground supply | |
PJ.4/XIN | 37 | 21 | 1 | 1 | I/O | General-purpose digital I/O |
Input terminal for crystal oscillator XT1 | ||||||
PJ.5/XOUT | 38 | 22 | 2 | 2 | I/O | General-purpose digital I/O |
Output terminal of crystal oscillator XT1 | ||||||
AVSS | 39 | 23 | 3 | 3 | Analog ground supply | |
AVCC | 40 | 24 | 4 | 4 | Analog power supply | |
QFN Pad | Pad | Pad | N/A | N/A | QFN package pad. Connection to VSS recommended. |