SLASE35C May   2014  – December 2017 MSP430FR5720 , MSP430FR5721 , MSP430FR5722 , MSP430FR5723 , MSP430FR5724 , MSP430FR5725 , MSP430FR5726 , MSP430FR5727 , MSP430FR5728 , MSP430FR5729

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram - RHA Package - MSP430FR5721, MSP430FR5723, MSP430FR5725, MSP430FR5727, MSP430FR5729
    2. 4.2 Pin Diagram - DA Package - MSP430FR5721, MSP430FR5723, MSP430FR5725, MSP430FR5727, MSP430FR5729
    3. 4.3 Pin Diagram - RGE Package - MSP430FR5720, MSP430FR5722, MSP430FR5724, MSP430FR5726, MSP430FR5728
    4. 4.4 Pin Diagram - PW Package - MSP430FR5720, MSP430FR5722, MSP430FR5724, MSP430FR5726, MSP430FR5728
    5. 4.5 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
    8. 5.8  Inputs - Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
    10. 5.10 Outputs - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
    11. 5.11 Output Frequency - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
    12. 5.12 Typical Characteristics - Outputs
    13. 5.13 Crystal Oscillator, XT1, Low-Frequency (LF) Mode
    14. 5.14 Crystal Oscillator, XT1, High-Frequency (HF) Mode
    15. 5.15 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    16. 5.16 DCO Frequencies
    17. 5.17 MODOSC
    18. 5.18 PMM, Core Voltage
    19. 5.19 PMM, SVS, BOR
    20. 5.20 Wake-up Times From Low-Power Modes
    21. 5.21 Timer_A
    22. 5.22 Timer_B
    23. 5.23 eUSCI (UART Mode) Clock Frequency
    24. 5.24 eUSCI (UART Mode)
    25. 5.25 eUSCI (SPI Master Mode) Clock Frequency
    26. 5.26 eUSCI (SPI Master Mode)
    27. 5.27 eUSCI (SPI Slave Mode)
    28. 5.28 eUSCI (I2C Mode)
    29. 5.29 10-Bit ADC, Power Supply and Input Range Conditions
    30. 5.30 10-Bit ADC, Timing Parameters
    31. 5.31 10-Bit ADC, Linearity Parameters
    32. 5.32 REF, External Reference
    33. 5.33 REF, Built-In Reference
    34. 5.34 REF, Temperature Sensor and Built-In VMID
    35. 5.35 Comparator_D
    36. 5.36 FRAM
    37. 5.37 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Functional Block Diagrams
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  FRAM
    9. 6.9  Memory Protection Unit (MPU)
    10. 6.10 Peripherals
      1. 6.10.1  Digital I/O
      2. 6.10.2  Oscillator and Clock System (CS)
      3. 6.10.3  Power-Management Module (PMM)
      4. 6.10.4  Hardware Multiplier (MPY)
      5. 6.10.5  Real-Time Clock (RTC_B)
      6. 6.10.6  Watchdog Timer (WDT_A)
      7. 6.10.7  System Module (SYS)
      8. 6.10.8  DMA Controller
      9. 6.10.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.10.10 TA0, TA1
      11. 6.10.11 TB0, TB1, TB2
      12. 6.10.12 ADC10_B
      13. 6.10.13 Comparator_D
      14. 6.10.14 CRC16
      15. 6.10.15 Shared Reference (REF)
      16. 6.10.16 Embedded Emulation Module (EEM)
      17. 6.10.17 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      6. 6.11.6  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P2 (P2.7) Input/Output With Schmitt Trigger
      8. 6.11.8  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      9. 6.11.9  Port P3 (P3.4 to P3.6) Input/Output With Schmitt Trigger
      10. 6.11.10 Port Port P3 (P3.7) Input/Output With Schmitt Trigger
      11. 6.11.11 Port Port P4 (P4.0) Input/Output With Schmitt Trigger
      12. 6.11.12 Port Port P4 (P4.1) Input/Output With Schmitt Trigger
      13. 6.11.13 Port Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
      14. 6.11.14 Port Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
  7. 7Device and Documentation Support
    1. 7.1  Getting Started
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Voltage applied at VCC to VSS –0.3 4.1 V
Voltage applied to any pin (excluding VCORE) (2) –0.3 VCC + 0.3 V
Diode current at any device pin ±2 mA
Maximum junction temperature, TJ 95 °C
Storage temperatureTstg(3) (4) (5) –55 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Data retention on FRAM cannot be ensured when exceeding the specified maximum storage temperature, Tstg.
(4) For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
(5) Programming of devices with user application code should only be performed after reflow or hand soldering. Factory programmed information, such as calibration values, are designed to withstand the temperatures reached in the current JEDEC J-STD-020 specification.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance.

5.3 Recommended Operating Conditions

Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage during program execution and FRAM programming (AVCC  = DVCC) (1) 2.0 3.6 V
VSS Supply voltage (AVSS = DVSS) 0 V
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 85 °C
CVCORE Required capacitor at VCORE(2) 470 nF
CVCC/ CVCORE Capacitor ratio of VCC to VCORE 10
fSYSTEM Processor frequency (maximum MCLK frequency)(3) No FRAM wait states(4),
2 V ≤ VCC ≤ 3.6 V		 0 8.0 MHz
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation.
(2) A capacitor tolerance of ±20% or better is required.
(3) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(4) When using manual wait state control, see the MSP430FR57xx Family User's Guide for recommended settings for common system frequencies.

5.4 Active Mode Supply Current Into VCC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted)(1) (2) (3)
PARAMETER EXECUTION MEMORY VCC Frequency (fMCLK = fSMCLK) UNIT
1 MHz 4 MHz 8 MHz
TYP MAX TYP MAX TYP MAX
IAM, FRAM_UNI(5) FRAM 3 V 0.27 0.58 1.0 mA
IAM,0%(6) FRAM
0% cache hit ratio		 3 V 0.42 0.73 1.2 1.6 2.2 2.8 mA
IAM,50%(6) (4) FRAM
50% cache hit ratio		 3 V 0.31 0.73 1.3 mA
IAM,66%(6) (4) FRAM
66% cache hit ratio		 3 V 0.27 0.58 1.0 mA
IAM,75%(6) (4) FRAM
75% cache hit ratio		 3 V 0.25 0.5 0.82 mA
IAM,100%(6) (4) FRAM
100% cache hit ratio		 3 V 0.2 0.43 0.3 0.55 0.42 0.8 mA
IAM, RAM(4) (7) RAM 3 V 0.2 0.4 0.35 0.55 0.55 0.75 mA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance are chosen to closely match the required 9 pF.
(3) Characterized with program executing typical data processing.
(4) See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best linear fit using the typical data shown in .
fACLK = 32786 Hz, fMCLK = fSMCLK at specified frequency. No peripherals active.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
(5) Program and data reside entirely in FRAM. No wait states enabled. DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK.
(6) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 25% ratio implies one of every four accesses is from cache, the remaining are FRAM accesses.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK. No wait states enabled.
(7) All execution is from RAM.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK.
MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 slas639_IAM_nowait_curves.gif Figure 5-1 Typical Active Mode Supply Currents, No Wait States

5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
PARAMETER VCC –40°C 25°C 60°C 85°C UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
ILPM0,1MHz Low-power mode 0 (3) (12) 2 V,
3 V		 166 175 190 225 µA
LPM0,8MHz Low-power mode 0 (4) (12) 2 V,
3 V		 170 177 244 195 225 360 µA
LPM0,24MHz Low-power mode 0 (5) (12) 2 V,
3 V		 274 285 340 315 340 455 µA
ILPM2 Low-power mode 2 (6) (13) 2 V,
3 V		 56 61 80 75 110 210 µA
ILPM3,XT1LF Low-power mode 3, crystal mode (7) (13) 2 V,
3 V		 3.4 6.4 15 18 48 150 µA
ILPM3,VLO Low-power mode 3, VLO mode (8) (13) 2 V,
3 V		 3.3 6.3 15 18 48 150 µA
ILPM4 Low-power mode 4 (9) (13) 2 V,
3 V		 2.9 5.9 15 18 48 150 µA
ILPM3.5 Low-power mode 3.5 (10) 2 V,
3 V		 1.3 1.5 2.2 1.9 2.8 5.0 µA
ILPM4.5 Low-power mode 4.5 (11) 2 V,
3 V		 0.3 0.32 0.66 0.38 0.57 2.55 µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK  = 1 MHz. DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz)
(4) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK  = 8 MHz. DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz)
(5) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK  = 24 MHz. DCORSEL = 1, DCOFSELx = 3 (fDCO = 24 MHz)
(6) Current for watchdog timer (clocked by ACLK) and RTC (clocked by XT1 LF mode) included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCORSEL = 0, DCOFSELx = 3, DCO bias generator enabled.
(7) Current for watchdog timer (clocked by ACLK) and RTC (clocked by XT1 LF mode) included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(8) Current for watchdog timer (clocked by ACLK) included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(9) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK =  fMCLK = fSMCLK = 0 MHz
(10) Internal regulator disabled. No data retention. RTC active clocked by XT1 LF mode.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM3.5), fDCO = fACLK =  fMCLK = fSMCLK = 0 MHz
(11) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK =  fMCLK = fSMCLK = 0 MHz
(12) Current for brownout, high-side supervisor (SVSH), and low-side supervisor (SVSL) included.
(13) Current for brownout and high-side supervisor (SVSH) included. Low-side supervisor (SVSL) disabled.

5.6 Thermal Resistance Characteristics

PARAMETER PACKAGE VALUE(1) UNIT
θJA Junction-to-ambient thermal resistance, still air(2) TSSOP-24 (PW) 78.8 °C/W
θJC(TOP) Junction-to-case (top) thermal resistance(3) 19.4 °C/W
θJB Junction-to-board thermal resistance(5) 36.7 °C/W
ΨJB Junction-to-board thermal characterization parameter 36.2 °C/W
ΨJT Junction-to-top thermal characterization parameter 0.5 °C/W
θJC(BOTTOM) Junction-to-case (bottom) thermal resistance(4) N/A °C/W
θJA Junction-to-ambient thermal resistance, still air(2) QFN-24 (RGE) 42.1 °C/W
θJC(TOP) Junction-to-case (top) thermal resistance(3) 38.8 °C/W
θJB Junction-to-board thermal resistance(5) 18.1 °C/W
ΨJB Junction-to-board thermal characterization parameter 18.0 °C/W
ΨJT Junction-to-top thermal characterization parameter 0.6 °C/W
θJC(BOTTOM) Junction-to-case (bottom) thermal resistance(4) 2.8 °C/W
θJA Junction-to-ambient thermal resistance, still air(2) SOIC-38 (DA) 74.5 °C/W
θJC(TOP) Junction-to-case (top) thermal resistance(3) 22.0 °C/W
θJB Junction-to-board thermal resistance(5) 40.7 °C/W
ΨJB Junction-to-board thermal characterization parameter 40.3 °C/W
ΨJT Junction-to-top thermal characterization parameter 0.9 °C/W
θJC(BOTTOM) Junction-to-case (bottom) thermal resistance(4) N/A °C/W
θJA Junction-to-ambient thermal resistance, still air(2) QFN-40 (RHA) 37.8 °C/W
θJC(TOP) Junction-to-case (top) thermal resistance(3) 27.4 °C/W
θJB Junction-to-board thermal resistance(5) 12.6 °C/W
ΨJB Junction-to-board thermal characterization parameter 12.6 °C/W
ΨJT Junction-to-top thermal characterization parameter 0.4 °C/W
θJC(BOTTOM) Junction-to-case (bottom) thermal resistance(4) 3.6 °C/W
(1) N/A = Not applicable
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

5.7 Schmitt-Trigger Inputs – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VIT+ Positive-going input threshold voltage 2 V 0.80 1.40 V
3 V 1.50 2.10
VIT– Negative-going input threshold voltage 2 V 0.45 1.10 V
3 V 0.75 1.65
Vhys Input voltage hysteresis (VIT+ – VIT–) 2 V 0.25 0.8 V
3 V 0.30 1.0
RPull Pullup or pulldown resistor For pullup: VIN = VSS
For pulldown: VIN = VCC 		20 35 50 kΩ
CI Input capacitance VIN = VSS or VCC 5 pF

5.8 Inputs – Ports P1 and P2 (1)
(P1.0 to P1.7, P2.0 to P2.7)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
t(int) External interrupt timing (2) External trigger pulse duration to set interrupt flag 2 V, 3 V 20 ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int).

5.9 Leakage Current – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(Px.x) High-impedance leakage current   (1) (2) 2 V, 3 V –50 50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.

5.10 Outputs – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VOH High-level output voltage I(OHmax) = –1 mA (1) 2 V VCC – 0.25 VCC V
I(OHmax) = –3 mA (2) VCC – 0.60 VCC
I(OHmax) = –2 mA (1) 3 V VCC – 0.25 VCC
I(OHmax) = –6 mA (2) VCC – 0.60 VCC
VOL Low-level output voltage I(OLmax) = 1 mA (1) 2 V VSS VSS + 0.25 V
I(OLmax) = 3 mA (2) VSS VSS + 0.60
I(OLmax) = 2 mA (1) 3 V VSS VSS + 0.25
I(OLmax) = 6 mA (2) VSS VSS + 0.60
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified.

5.11 Output Frequency – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
fPx.y Port output frequency (with load) Px.y (1) (2) 2 V 16 MHz
3 V 24
fPort_CLK Clock output frequency ACLK, SMCLK, or MCLK at configured output port,
CL = 20 pF, no DC loading (2) 		2 V 16 MHz
3 V 24
(1) A resistive divider with 2 × 1.6 kΩ   between VCC and VSS is used as load. The output is connected to the center tap of the divider. CL = 20 pF is connected from the output to VSS.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

5.12 Typical Characteristics – Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 slas639_IOL_2V.gif
VCC = 2.0 V Measured at Px.y
Figure 5-2 Typical Low-Level Output Current vs Low-Level Output Voltage
MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 slas639_IOL_3V.gif
VCC = 3.0 V Measured at Px.y
Figure 5-3 Typical Low-Level Output Current vs Low-Level Output Voltage
MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 slas639_IOH_2V.gif
VCC = 2.0 V Measured at Px.y
Figure 5-4 Typical High-Level Output Current vs High-Level Output Voltage
MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 slas639_IOH_3V.gif
VCC = 3.0 V Measured at Px.y
Figure 5-5 Typical High-Level Output Current vs High-Level Output Voltage

5.13 Crystal Oscillator, XT1, Low-Frequency (LF) Mode (5)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
ΔIVCC.LF Additional current consumption XT1 LF mode from lowest drive setting fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {1},
CL,eff = 9 pF, TA = 25°C,		 3 V 60 nA
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {2},
TA = 25°C, CL,eff = 9 pF		 3 V 90
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 12 pF		 3 V 140
fXT1,LF0 XT1 oscillator crystal frequency, LF mode XTS = 0, XT1BYPASS = 0 32768 Hz
fXT1,LF,SW XT1 oscillator logic-level square-wave input frequency, LF mode XTS = 0, XT1BYPASS = 1 (6) (7) 10 32.768 50 kHz
OALF Oscillation allowance for LF crystals (8) XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
fXT1,LF = 32768 Hz, CL,eff = 6 pF		 210 kΩ
XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
fXT1,LF = 32768 Hz, CL,eff = 12 pF		 300
Duty cycle, LF mode XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz		 30% 70%
fFault,LF Oscillator fault frequency, LF mode (4) XTS = 0 (3) 10 10000 Hz
tSTART,LF Start-up time, LF mode (9) fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
TA = 25°C, CL,eff = 6 pF		 3 V 1000 ms
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 12 pF		 1000
CL,eff Integrated effective load capacitance, LF mode (1) (2) XTS = 0 1 pF
(1) Requires external capacitors at both terminals.
(2) Values are specified by crystal manufacturers. Include parasitic bond and package capacitance (approximately 2 pF per pin). Recommended values supported are 6 pF, 9 pF, and 12 pF. Maximum shunt capacitance of 1.6 pF.
(3) Measured with logic-level input frequency but also applies to operation with crystals.
(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag.
(5) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
  • Keep the trace between the device and the crystal as short as possible.
  • Design a good ground plane around the oscillator pins.
  • Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
  • Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
  • Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
  • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(6) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this data sheet.
(7) Maximum frequency of operation of the entire device cannot be exceeded.
(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application:
  • For XT1DRIVE = {0}, CL,eff ≤ 6 pF.
  • For XT1DRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF.
  • For XT1DRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF.
  • For XT1DRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF.
(9) Includes start-up counter of 4096 clock cycles.

5.14 Crystal Oscillator, XT1, High-Frequency (HF) Mode (5)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IVCC,HF XT1 oscillator crystal current HF mode fOSC = 4 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
TA = 25°C, CL,eff = 16 pF		 3 V 175 µA
fOSC = 8 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {1},
TA = 25°C, CL,eff = 16 pF		 300
fOSC = 16 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {2},
TA = 25°C, CL,eff = 16 pF		 350
fOSC = 24 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 16 pF		 550
fXT1,HF0 XT1 oscillator crystal frequency, HF mode 0 XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0} (7) 		4 6 MHz
fXT1,HF1 XT1 oscillator crystal frequency, HF mode 1 XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {1} (7) 		6 10 MHz
fXT1,HF2 XT1 oscillator crystal frequency, HF mode 2 XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {2} (7) 		10 16 MHz
fXT1,HF3 XT1 oscillator crystal frequency, HF mode 3 XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {3} (7) 		16 24 MHz
fXT1,HF,SW XT1 oscillator logic-level square-wave input frequency, HF mode XTS = 1,
XT1BYPASS = 1 (6) (7) 		1 24 MHz
OAHF Oscillation allowance for HF crystals (8) XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0},
fXT1,HF = 4 MHz, CL,eff = 16 pF		 450 Ω
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {1},
fXT1,HF = 8 MHz, CL,eff = 16 pF		 320
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {2},
fXT1,HF = 16 MHz, CL,eff = 16 pF		 200
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {3},
fXT1,HF = 24 MHz, CL,eff = 16 pF		 200
tSTART,HF Start-up time, HF mode (9) fOSC = 4 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0},
TA = 25°C, CL,eff = 16 pF		 3 V 8 ms
fOSC = 24 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 16 pF		 2
CL,eff Integrated effective load capacitance (1) (2) XTS = 1 1 pF
Duty cycle, HF mode XTS = 1, Measured at ACLK,
fXT1,HF2 = 24 MHz		 40% 50% 60%
fFault,HF Oscillator fault frequency, HF mode (4) XTS = 1 (3) 145 900 kHz
(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.
(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF.
(3) Measured with logic-level input frequency but also applies to operation with crystals.
(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specificiations might set the flag.
(5) To improve EMI on the XT1 oscillator the following guidelines should be observed.
  • Keep the traces between the device and the crystal as short as possible.
  • Design a good ground plane around the oscillator pins.
  • Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
  • Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
  • Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
  • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(6) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this data sheet.
(7) Maximum frequency of operation of the entire device cannot be exceeded.
(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(9) Includes start-up counter of 4096 clock cycles.

5.15 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fVLO VLO frequency Measured at ACLK 2 V to 3.6 V 5 8.3 13 kHz
dfVLO/dT VLO frequency temperature drift Measured at ACLK (1) 2 V to 3.6 V 0.5 %/°C
dfVLO/dVCC VLO frequency supply voltage drift Measured at ACLK (2) 2 V to 3.6 V 4 %/V
fVLO,DC Duty cycle Measured at ACLK 2 V to 3.6 V 40% 50% 60%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(2.0 V to 3.6 V) – MIN(2.0 V to 3.6 V)) / MIN(2.0 V to 3.6 V) / (3.6 V – 2 V)

NOTE

In LPM3, the VLO frequency varies by up to ±6% (typical), due to bias current sampling. This frequency variation is not a violation VLO specifications (see Section 5.15).

5.16 DCO Frequencies

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC
TA 		MIN TYP MAX UNIT
fDCO,LO DCO frequency low, trimmed Measured at ACLK,
DCORSEL = 0		 2 V to 3.6 V
–40°C to 85°C		 5.37 ±3.5% MHz
2 V to 3.6 V
0°C to 50°C		 5.37 ±2.0%
fDCO,MID DCO frequency mid, trimmed Measured at ACLK,
DCORSEL = 0		 2 V to 3.6 V
–40°C to 85°C		 6.67 ±3.5% MHz
2 V to 3.6 V
0°C to 50°C		 6.67 ±2.0%
fDCO,HI DCO frequency high, trimmed Measured at ACLK,
DCORSEL = 0		 2 V to 3.6 V
–40°C to 85°C		 8 ±3.5% MHz
2 V to 3.6 V
0°C to 50°C		 8 ±2.0%
fDCO,DC Duty cycle Measured at ACLK, divide by 1,
No external divide, all DCO settings		 2 V to 3.6 V
–40°C to 85°C		 40% 50% 60%

5.17 MODOSC

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IMODOSC Current consumption Enabled 2 V to 3.6 V 44 80 µA
fMODOSC MODOSC frequency 2 V to 3.6 V 4.5 5.0 5.5 MHz
fMODOSC,DC Duty cycle Measured at ACLK, divide by 1 2 V to 3.6 V 40% 50% 60%

5.18 PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCORE(AM) Core voltage, active mode 2 V ≤ DVCC ≤ 3.6 V 1.5 V
VCORE(LPM) Core voltage, low-current mode 2 V ≤ DVCC ≤ 3.6 V 1.5 V

5.19 PMM, SVS, BOR

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISVSH,AM SVSH current consumption, active mode VCC = 3.6 V 5 µA
ISVSH,LPM SVSH current consumption, low power modes VCC = 3.6 V 0.8 1.5 µA
VSVSH- SVSH on voltage level, falling supply voltage 1.83 1.88 1.93 V
VSVSH+ SVSH off voltage level, rising supply voltage 1.88 1.93 1.98 V
tPD,SVSH, AM SVSH propagation delay, active mode dVCC/dt = 10 mV/µs 10 µs
tPD,SVSH, LPM SVSH propagation delay, low power modes dVCC/dt = 1 mV/µs 30 µs
ISVSL SVSL current consumption 0.3 0.5 µA
VSVSL– SVSL on voltage level 1.42 V
VSVSL+ SVSL off voltage level 1.47 V

5.20 Wake-up Times From Low-Power Modes

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC
TA 		MIN TYP MAX UNIT
tWAKE-UP LPM0 Wake-up time from LPM0 to active mode (1) 2 V, 3 V
–40°C to 85°C		 0.58 1 µs
tWAKE-UP LPM12 Wake-up time from LPM1, LPM2 to active mode (1) 2 V, 3 V
–40°C to 85°C		 12 25 µs
tWAKE-UP LPM34 Wake-up time from LPM3 or LPM4 to active mode (1) 2 V, 3 V
–40°C to 85°C		 78 120 µs
tWAKE-UP LPMx.5 Wake-up time from LPM3.5 or LPM4.5 to active mode (1) 2 V, 3 V
0°C to 85°C		 310 575 µs
2 V, 3 V
–40°C to 85°C		 310 1100
tWAKE-UP RESET Wake-up time from RST to active mode (2) VCC stable
 2 V, 3 V
–40°C to 85°C		 230 280 µs
tWAKE-UP BOR Wake-up time from BOR or power-up to active mode dVCC/dt = 2400 V/s 2 V, 3 V
–40°C to 85°C		 1.6 ms
tRESET Pulse duration required at RST/NMI terminal to accept a reset event(3) 2 V, 3 V
–40°C to 85°C		 4 ns
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first instruction of the user program is executed.
(2) The wake-up time is measured from the rising edge of the RST signal until the first instruction of the user program is executed.
(3) Meeting or exceeding this time makes sures a reset event occurs. Pulses shorter than this minimum time may or may not cause a reset event to occur.

5.21 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fTA Timer_A input clock frequency Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ±10%		 2 V, 3 V 8 MHz
tTA,cap Timer_A capture timing All capture inputs, Minimum pulse duration required for capture 2 V, 3 V 20 ns

5.22 Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fTB Timer_B input clock frequency Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ±10%		 2 V, 3 V 8 MHz
tTB,cap Timer_B capture timing All capture inputs, Minimum pulse duration required for capture 2 V, 3 V 20 ns

5.23 eUSCI (UART Mode) Clock Frequency

PARAMETER CONDITIONS VCC MIN TYP MAX UNIT
feUSCI eUSCI input clock frequency Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%		 fSYSTEM MHz
fBITCLK BITCLK clock frequency
(equals baud rate in MBaud)		 5 MHz

5.24 eUSCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
tt UART receive deglitch time(1) UCGLITx = 0 2 V, 3 V 5 15 20 ns
UCGLITx = 1 20 45 60
UCGLITx = 2 35 80 120
UCGLITx = 3 50 110 180
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time.

5.25 eUSCI (SPI Master Mode) Clock Frequency

PARAMETER CONDITIONS VCC MIN TYP MAX UNIT
feUSCI eUSCI input clock frequency Internal: SMCLK, ACLK
Duty cycle = 50% ±10%		 fSYSTEM MHz

5.26 eUSCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
tSTE,LEAD STE lead time, STE active to clock UCSTEM = 0,
UCMODEx = 01 or 10		 2 V, 3 V 1 UCxCLK cycles
UCSTEM = 1,
UCMODEx = 01 or 10		 2 V, 3 V 1
tSTE,LAG STE lag time, Last clock to STE inactive UCSTEM = 0,
UCMODEx = 01 or 10		 2 V, 3 V 1 UCxCLK cycles
UCSTEM = 1,
UCMODEx = 01 or 10		 2 V, 3 V 1
tSTE,ACC STE access time, STE active to SIMO data out UCSTEM = 0,
UCMODEx = 01 or 10		 2 V, 3 V 55 ns
UCSTEM = 1,
UCMODEx = 01 or 10		 2 V, 3 V 35
tSTE,DIS STE disable time, STE inactive to SIMO high impedance UCSTEM = 0,
UCMODEx = 01 or 10		 2 V, 3 V 40 ns
UCSTEM = 1,
UCMODEx = 01 or 10		 2 V, 3 V 30
tSU,MI SOMI input data setup time 2 V 35 ns
3 V 35
tHD,MI SOMI input data hold time 2 V 0 ns
3 V 0
tVALID,MO SIMO output data valid time (2) UCLK edge to SIMO valid,
CL = 20 pF		 2 V 30 ns
3 V 30
tHD,MO SIMO output data hold time (3) CL = 20 pF 2 V 0 ns
3 V 0
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-6 and Figure 5-7.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-6 and Figure 5-7.
MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 slas639-eUSCI_master_CKPH0.gif Figure 5-6 SPI Master Mode, CKPH = 0
MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 slas639-eUSCI_master_CKPH1.gif Figure 5-7 SPI Master Mode, CKPH = 1

5.27 eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
tSTE,LEAD STE lead time, STE active to clock 2 V 7 ns
3 V 7
tSTE,LAG STE lag time, Last clock to STE inactive 2 V 0 ns
3 V 0
tSTE,ACC STE access time, STE active to SOMI data out 2 V 65 ns
3 V 40
tSTE,DIS STE disable time, STE inactive to SOMI high impedance 2 V 40 ns
3 V 35
tSU,SI SIMO input data setup time 2 V 2 ns
3 V 2
tHD,SI SIMO input data hold time 2 V 5 ns
3 V 5
tVALID,SO SOMI output data valid time (2) UCLK edge to SOMI valid,
CL = 20 pF		 2 V 30 ns
3 V 30
tHD,SO SOMI output data hold time (3) CL = 20 pF 2 V 4 ns
3 V 4
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-8 and Figure 5-9.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-8 and Figure 5-9.
MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 slas639-eUSCI_slave_CKPH0.gif Figure 5-8 SPI Slave Mode, CKPH = 0
MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 slas639-eUSCI_slave_CKPH1.gif Figure 5-9 SPI Slave Mode, CKPH = 1

5.28 eUSCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-10)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
feUSCI eUSCI input clock frequency Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%		 fSYSTEM MHz
fSCL SCL clock frequency 2 V, 3 V 0 400 kHz
tHD,STA Hold time (repeated) START fSCL = 100 kHz 2 V, 3 V 4.0 µs
fSCL > 100 kHz 0.6
tSU,STA Setup time for a repeated START fSCL = 100 kHz 2 V, 3 V 4.7 µs
fSCL > 100 kHz 0.6
tHD,DAT Data hold time 2 V, 3 V 0 ns
tSU,DAT Data setup time 2 V, 3 V 250 ns
tSU,STO Setup time for STOP fSCL = 100 kHz 2 V, 3 V 4.0 µs
fSCL > 100 kHz 0.6
tSP Pulse duration of spikes suppressed by input filter UCGLITx = 0 2 V, 3 V 50 600 ns
UCGLITx = 1 25 300
UCGLITx = 2 12.5 150
UCGLITx = 3 6.25 75
tTIMEOUT Clock low time-out UCCLTOx = 1 2 V, 3 V 27 ms
UCCLTOx = 2 30
UCCLTOx = 3 33
MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 slas639-017.gif Figure 5-10 I2C Mode Timing

5.29 10-Bit ADC, Power Supply and Input Range Conditions

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V		 2.0 3.6 V
V(Ax) Analog input voltage range All ADC10 pins 0 AVCC V
IADC10_A Operating supply current into AVCC terminal, reference current not included fADC10CLK = 5 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0		 2 V 90 140 µA
3 V 100 160
CI Input capacitance Only one terminal Ax can be selected at one time from the pad to the ADC10_A capacitor array including wiring and pad 2.2 V 6 8 pF
RI Input MUX ON resistance AVCC ≥ 2 V, 0 V ≤ VAx ≤ AVCC 36 kΩ

5.30 10-Bit ADC, Timing Parameters

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fADC10CLK For specified performance of ADC10 linearity parameters 2 V to 3.6 V 0.45 5 5.5 MHz
fADC10OSC Internal ADC10 oscillator (MODOSC) ADC10DIV = 0, fADC10CLK = fADC10OSC 2 V to 3.6 V 4.5 4.5 5.5 MHz
tCONVERT Conversion time REFON = 0, Internal oscillator,
12 ADC10CLK cycles, 10-bit mode,
fADC10OSC = 4.5 MHz to 5.5 MHz		 2 V to 3.6 V 2.18 2.67 µs
External fADC10CLK from ACLK, MCLK, or SMCLK, ADC10SSEL ≠ 0 2 V to 3.6 V   (1)
tADC10ON Turnon settling time of the ADC The error in a conversion started after tADC10ON is less than ±0.5 LSB,
Reference and input signal already settled		 100 ns
tSample Sampling time RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF,
Approximately eight Tau (τ) are required to get an error of less than ±0.5 LSB		 2 V 1.5 µs
3 V 2.0
(1) 12 × ADC10DIV × 1/fADC10CLK

5.31 10-Bit ADC, Linearity Parameters

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
EI Integral linearity error 1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V 2 V to 3.6 V –1.4 1.4 LSB
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC –1.1 1.1
ED Differential linearity error (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–) 2 V to 3.6 V –1 1 LSB
EO Offset error (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–) 2 V to 3.6 V –6.5 6.5 mV
EG Gain error, external reference (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–) 2 V to 3.6 V –1.2 1.2 LSB
Gain error, internal reference (1) –4% 4%
ET Total unadjusted error, external reference (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–) 2 V to 3.6 V –2 2 LSB
Total unadjusted error, internal reference (1) –4% 4%
(1) Error is dominated by the internal reference.

5.32 REF, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VeREF+ Positive external reference voltage input VeREF+ > VeREF– (2) 1.4 AVCC V
VeREF– Negative external reference voltage input VeREF+ > VeREF– (3) 0 1.2 V
(VeREF+ –
VREF–/VeREF–)		 Differential external reference voltage input VeREF+ > VeREF– (4) 1.4 AVCC V
IVeREF+,
IVeREF– 		Static input current 1.4 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 1h,
Conversion rate 200 ksps		 2.2 V, 3 V –6 6 µA
1.4 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 8h,
Conversion rate 20 ksps		 2.2 V, 3 V –1 1
CVREF+,
CVREF- 		Capacitance at VREF+ or VREF- terminal(5) 10 µF
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_B. Also see the MSP430FR57xx Family User's Guide.

5.33 REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF+ Positive built-in reference voltage output REFVSEL = {2} for 2.5 V, REFON = 1 3 V 2.4 2.5 2.6 V
REFVSEL = {1} for 2 V, REFON = 1 3 V 1.92 2.0 2.08
REFVSEL = {0} for 1.5 V, REFON = 1 3 V 1.44 1.5 1.56
AVCC(min) AVCC minimum voltage, Positive built-in reference active REFVSEL = {0} for 1.5 V 2.0 V
REFVSEL = {1} for 2 V 2.2
REFVSEL = {2} for 2.5 V 2.7
IREF+ Operating supply current into AVCC terminal (1) fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0		 3 V 33 45 µA
TREF+ Temperature coefficient of built-in reference REFVSEL = (0, 1, 2}, REFON = 1 ±35 ppm/ °C
PSRR_DC Power supply rejection ratio (DC) AVCC = AVCC (min) - AVCC(max),
TA = 25°C, REFON = 1,
REFVSEL = (0} for 1.5 V		 1600 µV/V
AVCC = AVCC (min) - AVCC(max),
TA = 25°C, REFON = 1,
REFVSEL = (1} for 2 V		 1900
AVCC = AVCC (min) - AVCC(max),
TA = 25°C, REFON = 1,
REFVSEL = (2} for 2.5 V		 3600
tSETTLE Settling time of reference voltage (2) AVCC = AVCC (min) - AVCC(max),
REFVSEL = (0, 1, 2}, REFON = 0 → 1		 30 µs
(1) The internal reference current is supplied by terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
(2) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.

5.34 REF, Temperature Sensor and Built-In VMID

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VSENSOR See (1) ADC10ON = 1, INCH = 0Ah,
TA = 0°C		 2 V, 3 V 790 mV
TCSENSOR ADC10ON = 1, INCH = 0Ah 2 V, 3 V 2.55 mV/°C
tSENSOR(sample) Sample time required if channel 10 is selected (2) ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB		 2 V 30 µs
3 V 30
VMID AVCC divider at channel 11 ADC10ON = 1, INCH = 0Bh,
VMID is ~0.5 × VAVCC 		2 V 0.97 1.0 1.03 V
3 V 1.46 1.5 1.54
tVMID(sample) Sample time required if channel 11 is selected (3) ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB		 2 V, 3 V 1000 ns
(1) The temperature sensor offset can vary significantly. A single-point calibration is recommended to minimize the offset error of the built-in temperature sensor.
(2) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
(3) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 slas639-018.gif Figure 5-11 Typical Temperature Sensor Voltage

5.35 Comparator_D

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpd Propagation delay,
AVCC = 2 V to 3.6 V		 Overdrive = 10 mV,
VIN- = (VIN+ – 400 mV) to (VIN+ + 10 mV)		 50 100 200 ns
Overdrive = 100 mV,
VIN- = (VIN+ – 400 mV) to (VIN+ + 100 mV)		 80
Overdrive = 250 mV,
(VIN+ – 400 mV) to (VIN+ + 250 mV)		 50
tfilter Filter timer added to the propagation delay of the comparator CDF = 1, CDFDLY = 00 0.3 0.5 0.9 µs
CDF = 1, CDFDLY = 01 0.5 0.9 1.5
CDF = 1, CDFDLY = 10 0.9 1.6 2.8
CDF = 1, CDFDLY = 11 1.6 3.0 5.5
Voffset Input offset AVCC = 2 V to 3.6 V –20 20 mV
Vic Common mode input range AVCC = 2 V to 3.6 V 0 AVCC - 1 V
Icomp(AVCC) Comparator only CDON = 1, AVCC = 2 V to 3.6 V 29 34 µA
Iref(AVCC) Reference buffer and R‑ladder CDREFLx = 01, AVCC = 2 V to 3.6 V 20 24 µA
tenable,comp Comparator enable time CDON = 0 to CDON = 1,
AVCC = 2 V to 3.6 V		 1.1 2.0 µs
tenable,rladder Resistor ladder enable time CDON = 0 to CDON = 1,
AVCC = 2 V to 3.6 V		 1.1 2.0 µs
VCB_REF Reference voltage for a tap VIN = voltage input to the R-ladder,
n = 0 to 31		 VIN × (n + 0.5) / 32 VIN ×
(n + 1)
/ 32		 VIN × (n + 1.5) / 32 V

5.36 FRAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DVCC(WRITE) Write supply voltage 2.0 3.6 V
tWRITE Word or byte write time 120 ns
tACCESS Read access time (1) 60 ns
tPRECHARGE Precharge time (1) 60 ns
tCYCLE Cycle time, read or write operation (1) 120 ns
Read and write endurance 1015 cycles
tRetention Data retention duration TJ = 25°C 100 years
TJ = 70°C 40
TJ = 85°C 10
(1) When using manual wait state control, see the MSP430FR57xx Family User's Guide for recommended settings for common system frequencies.

5.37 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VCC MIN TYP MAX UNIT
fSBW Spy-Bi-Wire input frequency 2 V, 3 V 0 20 MHz
tSBW,Low Spy-Bi-Wire low clock pulse duration 2 V, 3 V 0.025 15 µs
tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) 2 V, 3 V 1 µs
tSBW,Rst Spy-Bi-Wire return to normal operation time 19 35 µs
fTCK TCK input frequency, 4-wire JTAG (2) 2 V 0 5 MHz
3 V 0 10
Rinternal Internal pulldown resistance on TEST 2 V, 3 V 20 35 50 kΩ
(1) Tools that access the Spy-Bi-Wire and BSL interfaces must wait for the tSBW,En time after the first transition of the TEST/SBWTCK pin (low to high), before the second transition of the pin (high to low) during the entry sequence.
(2) fTCK may be restricted to meet the timing requirements of the module selected.