SLAS639L July 2011 – December 2017 MSP430FR5730 , MSP430FR5731 , MSP430FR5732 , MSP430FR5733 , MSP430FR5734 , MSP430FR5735 , MSP430FR5736 , MSP430FR5737 , MSP430FR5738 , MSP430FR5739
PRODUCTION DATA.
CAUTION | These products use FRAM nonvolatile memory technology. FRAM retention is sensitive to extreme temperatures, such as those experienced during reflow or hand soldering. See Absolute Maximum Ratings for more information. |
CAUTION | System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturb of data or code memory. See MSP430™ System-Level ESD Considerations for more information. |
The TI MSP430FR573x family of ultra-low-power microcontrollers consists of multiple devices that feature embedded FRAM nonvolatile memory, ultra-low-power 16-bit MSP430™ CPU, and different peripherals targeted for various applications. The architecture, FRAM, and peripherals, combined with seven low-power modes, are optimized to achieve extended battery life in portable and wireless sensing applications. FRAM is a new nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and reliability of flash, all at lower total power consumption. Peripherals include a 10-bit ADC, a 16-channel comparator with voltage reference generation and hysteresis capabilities, three enhanced serial channels capable of I2C, SPI, or UART protocols, an internal DMA, a hardware multiplier, an RTC, five 16-bit timers, and digital I/Os.
PART NUMBER | PACKAGE | BODY SIZE(2) |
---|---|---|
MSP430FR5739RHA | VQFN (40) | 6 mm × 6 mm |
MSP430FR5739DA | TSSOP (38) | 12.5 mm × 6.2 mm |
MSP430FR5738RGE | VQFN (24) | 4 mm × 4 mm |
MSP430FR5738PW | TSSOP (28) | 9.7 mm × 4.4 mm |
MSP430FR5738YQD | DSBGA (24) | 2 mm × 2 mm |
Figure 1-1 shows the functional block diagram for the MSP430FR5731, MSP430FR5735, and MSP430FR5739 devices in the RHA package. For the functional block diagrams for all device variants and package options, see Section 6.1.
Changes from October 1, 2016 to December 5, 2017
Table 3-1 summarizes the available family members.
DEVICE | FRAM (KB) |
SRAM (KB) |
SYSTEM CLOCK (MHz) |
ADC10_B | Comp_D | Timer_A(1) | Timer_B(2) | eUSCI | I/O | PACKAGE | |
---|---|---|---|---|---|---|---|---|---|---|---|
Channel A: UART, IrDA, SPI |
Channel B: SPI, I2C |
||||||||||
MSP430FR5739 | 16 | 1 | 24 | 12 ext, 2 int ch. | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5738 | 16 | 1 | 24 | 6 ext, 2 int ch. | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
8 ext, 2 int ch. | 12 ch. | 21 | PW | ||||||||
6 ext, 2 int ch. | 10 ch. | 17 | YQD | ||||||||
MSP430FR5737 | 16 | 1 | 24 | – | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5736 | 16 | 1 | 24 | – | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
12 ch. | 21 | PW | |||||||||
MSP430FR5735 | 8 | 1 | 24 | 12 ext, 2 int ch. | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5734 | 8 | 1 | 24 | 6 ext, 2 int ch. | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
8 ext, 2 int ch. | 12 ch. | 21 | PW | ||||||||
MSP430FR5733 | 8 | 1 | 24 | – | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5732 | 8 | 1 | 24 | – | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
12 ch. | 21 | PW | |||||||||
MSP430FR5731 | 4 | 1 | 24 | 12 ext, 2 int ch. | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5730 | 4 | 1 | 24 | 6 ext, 2 int ch. | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
8 ext, 2 int ch. | 12 ch. | 21 | PW |
For information about other devices in this family of products or related products, see the following links.
Figure 4-1 shows the pin diagram for the MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, and MSP430FR5739 devices in the 40-pin RHA package.
NOTE:
Exposed thermal pad connection to VSS recommended.Figure 4-2 shows the pin diagram for the MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, and MSP430FR5739 devices in the 38-pin DA package.
Figure 4-3 shows the pin diagram for the MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, and MSP430FR5738 devices in the 24-pin RGE package.
NOTE:
Exposed thermal pad connection to VSS recommended.Figure 4-4 shows the pin diagram for the MSP430FR5738 device in the 24-pin YQD package,
Figure 4-5 shows the pin diagram for the MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, and MSP430FR5738 devices in the 28-pin PW package.
Table 4-1 describes the signals for all device variants and packages.
TERMINAL | I/O (1) | DESCRIPTION | |||||
---|---|---|---|---|---|---|---|
NAME | NO. | ||||||
RHA | RGE | DA | PW | YQD | |||
P1.0/TA0.1/DMAE0/ RTCCLK/A0/CD0/VeREF- | 1 | 1 | 5 | 5 | C2 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TA0 CCR1 capture: CCI1A input, compare: Out1 | |||||||
External DMA trigger | |||||||
RTC clock calibration output | |||||||
Analog input A0 – ADC (not available on devices without ADC) | |||||||
Comparator_D input CD0 | |||||||
External applied reference voltage (not available on devices without ADC) | |||||||
P1.1/TA0.2/TA1CLK/ CDOUT/A1/CD1/VeREF+ | 2 | 2 | 6 | 6 | D1 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TA0 CCR2 capture: CCI2A input, compare: Out2 | |||||||
TA1 input clock | |||||||
Comparator_D output | |||||||
Analog input A1 – ADC (not available on devices without ADC) | |||||||
Comparator_D input CD1 | |||||||
Input for an external reference voltage to the ADC (not available on devices without ADC) | |||||||
P1.2/TA1.1/TA0CLK/ CDOUT/A2/CD2 | 3 | 3 | 7 | 7 | C1 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TA1 CCR1 capture: CCI1A input, compare: Out1 | |||||||
TA0 input clock | |||||||
Comparator_D output | |||||||
Analog input A2 – ADC (not available on devices without ADC) | |||||||
Comparator_D input CD2 | |||||||
P3.0/A12/CD12 | 4 | N/A | 8 | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD) |
Analog input A12 – ADC (not available on devices without ADC or package options PW, RGE, YQD) | |||||||
Comparator_D input CD12 (not available on package options PW, RGE, YQD) | |||||||
P3.1/A13/CD13 | 5 | N/A | 9 | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD) |
Analog input A13 – ADC (not available on devices without ADC or package options PW, RGE, YQD) | |||||||
Comparator_D input CD13 (not available on package options PW, RGE, YQD) | |||||||
P3.2/A14/CD14 | 6 | N/A | 10 | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD) |
Analog input A14 – ADC (not available on devices without ADC or package options PW, RGE, YQD) | |||||||
Comparator_D input CD14 (not available on package options PW, RGE, YQD) | |||||||
P3.3/A15/CD15 | 7 | N/A | 11 | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD) |
Analog input A15 – ADC (not available on devices without ADC or package options PW, RGE, YQD) | |||||||
Comparator_D input CD15 (not available on package options PW, RGE, YQD) | |||||||
P1.3/TA1.2/UCB0STE/ A3/CD3 | 8 | 4 | 12 | 8 | B1 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TA1 CCR2 capture: CCI2A input, compare: Out2 | |||||||
Slave transmit enable – eUSCI_B0 SPI mode | |||||||
Analog input A3 – ADC (not available on devices without ADC) | |||||||
Comparator_D input CD3 | |||||||
P1.4/TB0.1/UCA0STE/ A4/CD4 | 9 | 5 | 13 | 9 | B2 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB0 CCR1 capture: CCI1A input, compare: Out1 | |||||||
Slave transmit enable – eUSCI_A0 SPI mode | |||||||
Analog input A4 – ADC (not available on devices without ADC) | |||||||
Comparator_D input CD4 | |||||||
P1.5/TB0.2/UCA0CLK/ A5/CD5 | 10 | 6 | 14 | 10 | A1 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB0 CCR2 capture: CCI2A input, compare: Out2 | |||||||
Clock signal input – eUSCI_A0 SPI slave mode, Clock signal output – eUSCI_A0 SPI master mode |
|||||||
Analog input A5 – ADC (not available on devices without ADC) | |||||||
Comparator_D input CD5 | |||||||
PJ.0/TDO/TB0OUTH/ SMCLK/CD6 (4) | 11 | 7 | 15 | 11 | C3 | I/O | General-purpose digital I/O |
Test data output port | |||||||
Switch all PWM outputs high impedance input – TB0 | |||||||
SMCLK output | |||||||
Comparator_D input CD6 | |||||||
PJ.1/TDI/TCLK/TB1OUTH/ MCLK/CD7 (4) | 12 | 8 | 16 | 12 | A2 | I/O | General-purpose digital I/O |
Test data input or test clock input | |||||||
Switch all PWM outputs high impedance input – TB1 (not available on devices without TB1) | |||||||
MCLK output | |||||||
Comparator_D input CD7 | |||||||
PJ.2/TMS/TB2OUTH/ ACLK/CD8 (4) | 13 | 9 | 17 | 13 | B3 | I/O | General-purpose digital I/O |
Test mode select | |||||||
Switch all PWM outputs high impedance input – TB2 (not available on devices without TB2) | |||||||
ACLK output | |||||||
Comparator_D input CD8 | |||||||
PJ.3/TCK/CD9 (4) | 14 | 10 | 18 | 14 | A3 | I/O | General-purpose digital I/O |
Test clock | |||||||
Comparator_D input CD9 | |||||||
P4.0/TB2.0 | 15 | N/A | N/A | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD) |
TB2 CCR0 capture: CCI0B input, compare: Out0 (not available on devices without TB2 or package options DA, PW, RGE, YQD) | |||||||
P4.1 | 16 | N/A | N/A | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options DA, PW, RGE, YQD) |
P2.5/TB0.0/UCA1TXD/ UCA1SIMO | 17 | N/A | 19 | 15 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB0 CCR0 capture: CCI0A input, compare: Out0 | |||||||
Transmit data – eUSCI_A1 UART mode, Slave in, master out – eUSCI_A1 SPI mode (not available on devices without UCSI_A1) | |||||||
P2.6/TB1.0/UCA1RXD/ UCA1SOMI | 18 | N/A | 20 | 16 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB1) | |||||||
Receive data – eUSCI_A1 UART mode, Slave out, master in – eUSCI_A1 SPI mode (not available on devices without UCSI_A1) | |||||||
TEST/SBWTCK (4) (3) | 19 | 11 | 21 | 17 | A4 | I | Test mode pin – enable JTAG pins |
Spy-Bi-Wire input clock | |||||||
RST/NMI/SBWTDIO (4) (3) | 20 | 12 | 22 | 18 | B4 | I/O | Reset input active low |
Non-maskable interrupt input | |||||||
Spy-Bi-Wire data input/output | |||||||
P2.0/TB2.0/UCA0TXD/ UCA0SIMO/TB0CLK/ ACLK(3) | 21 | 13 | 23 | 19 | A5 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB2 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB2) | |||||||
Transmit data – eUSCI_A0 UART mode | |||||||
Slave in, master out – eUSCI_A0 SPI mode | |||||||
TB0 clock input | |||||||
ACLK output | |||||||
P2.1/TB2.1/UCA0RXD/ UCA0SOMI/TB0.0(3) | 22 | 14 | 24 | 20 | C4 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB2 CCR1 capture: CCI1A input, compare: Out1 (not available on devices without TB2) | |||||||
Receive data – eUSCI_A0 UART mode | |||||||
Slave out, master in – eUSCI_A0 SPI mode | |||||||
TB0 CCR0 capture: CCI0A input, compare: Out0 | |||||||
P2.2/TB2.2/UCB0CLK/ TB1.0 | 23 | 15 | 25 | 21 | B5 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB2 CCR2 capture: CCI2A input, compare: Out2 (not available on devices without TB2) | |||||||
Clock signal input – eUSCI_B0 SPI slave mode, Clock signal output – eUSCI_B0 SPI master mode |
|||||||
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB1) | |||||||
P3.4/TB1.1/TB2CLK/ SMCLK | 24 | N/A | 26 | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD) |
TB1 CCR1 capture: CCI1B input, compare: Out1 (not available on devices without TB1) | |||||||
TB2 clock input (not available on devices without TB2 or package options PW, RGE, YQD) | |||||||
SMCLK output (not available on package options PW, RGE, YQD) | |||||||
P3.5/TB1.2/CDOUT | 25 | N/A | 27 | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD) |
TB1 CCR2 capture: CCI2B input, compare: Out2 (not available on devices without TB1) | |||||||
Comparator_D output (not available on package options PW, RGE, YQD) | |||||||
P3.6/TB2.1/TB1CLK | 26 | N/A | 28 | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD) |
TB2 CCR1 capture: CCI1B input, compare: Out1 (not available on devices without TB2) | |||||||
TB1 clock input (not available on devices without TB1 or package options PW, RGE, YQD) | |||||||
P3.7/TB2.2 | 27 | N/A | 29 | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD) |
TB2 CCR2 capture: CCI2B input, compare: Out2 (not available on devices without TB2 or package options PW, RGE, YQD) | |||||||
P1.6/TB1.1/UCB0SIMO/ UCB0SDA/TA0.0 | 28 | 16 | 30 | 22 | D5 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB1 CCR1 capture: CCI1A input, compare: Out1 (not available on devices without TB1) | |||||||
Slave in, master out – eUSCI_B0 SPI mode | |||||||
I2C data – eUSCI_B0 I2C mode | |||||||
TA0 CCR0 capture: CCI0A input, compare: Out0 | |||||||
P1.7/TB1.2/UCB0SOMI/ UCB0SCL/TA1.0 | 29 | 17 | 31 | 23 | C5 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB1 CCR2 capture: CCI2A input, compare: Out2 (not available on devices without TB1) | |||||||
Slave out, master in – eUSCI_B0 SPI mode | |||||||
I2C clock – eUSCI_B0 I2C mode | |||||||
TA1 CCR0 capture: CCI0A input, compare: Out0 | |||||||
VCORE (2) | 30 | 18 | 32 | 24 | E5 | Regulated core power supply (internal use only, no external current loading) | |
DVSS | 31 | 19 | 33 | 25 | D4 | Digital ground supply | |
DVCC | 32 | 20 | 34 | 26 | E4 | Digital power supply | |
P2.7 | 33 | N/A | 35 | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
P2.3/TA0.0/UCA1STE/ A6/CD10 | 34 | N/A | 36 | 27 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options RGE, YQD) |
TA0 CCR0 capture: CCI0B input, compare: Out0 (not available on package options RGE, YQD) | |||||||
Slave transmit enable – eUSCI_A1 SPI mode (not available on devices without eUSCI_A1) | |||||||
Analog input A6 – ADC (not available on devices without ADC) | |||||||
Comparator_D input CD10 (not available on package options RGE, YQD) | |||||||
P2.4/TA1.0/UCA1CLK/ A7/CD11 | 35 | N/A | 37 | 28 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options RGE, YQD) |
TA1 CCR0 capture: CCI0B input, compare: Out0 (not available on package options RGE, YQD) | |||||||
Clock signal input – eUSCI_A1 SPI slave mode, Clock signal output – eUSCI_A1 SPI master mode (not available on devices without eUSCI_A1) | |||||||
Analog input A7 – ADC (not available on devices without ADC) | |||||||
Comparator_D input CD11 (not available on package options RGE, YQD) | |||||||
AVSS | 36 | N/A | 38 | N/A | N/A | Analog ground supply | |
PJ.4/XIN | 37 | 21 | 1 | 1 | E3 | I/O | General-purpose digital I/O |
Input terminal for crystal oscillator XT1 | |||||||
PJ.5/XOUT | 38 | 22 | 2 | 2 | E2 | I/O | General-purpose digital I/O |
Output terminal of crystal oscillator XT1 | |||||||
AVSS | 39 | 23 | 3 | 3 | D3 | Analog ground supply | |
AVCC | 40 | 24 | 4 | 4 | D2 | Analog power supply | |
QFN Pad | Pad | Pad | N/A | N/A | N/A | QFN package pad. Connection to VSS recommended. |
MIN | MAX | UNIT | |
---|---|---|---|
Voltage applied at VCC to VSS | –0.3 | 4.1 | V |
Voltage applied to any pin (excluding VCORE) (2) | –0.3 | VCC + 0.3 | V |
Diode current at any device pin | ±2 | mA | |
Maximum junction temperature, TJ | 95 | °C | |
Storage temperatureTstg(3) (4) (5) | –55 | 125 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) | ±1000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) | ±250 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage during program execution and FRAM programming (AVCC = DVCC) (1) | 2.0 | 3.6 | V | ||
VSS | Supply voltage (AVSS = DVSS) | 0 | V | |||
TA | Operating free-air temperature | –40 | 85 | °C | ||
TJ | Operating junction temperature | –40 | 85 | °C | ||
CVCORE | Required capacitor at VCORE(2) | 470 | nF | |||
CVCC/ CVCORE | Capacitor ratio of VCC to VCORE | 10 | ||||
fSYSTEM | Processor frequency (maximum MCLK frequency)(3) | No FRAM wait states(4), 2 V ≤ VCC ≤ 3.6 V |
0 | 8.0 | MHz | |
With FRAM wait states(4), NACCESS = {2}, NPRECHG = {1}, 2 V ≤ VCC ≤ 3.6 V |
0 | 24.0 |
PARAMETER | EXECUTION MEMORY | VCC | Frequency (fMCLK = fSMCLK)(5) | UNIT | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 MHz | 4 MHz | 8 MHz | 16 MHz | 20 MHz | 24 MHz | ||||||||||
TYP | MAX | TYP | MAX | TYP | MAX | TYP | MAX | TYP | MAX | TYP | MAX | ||||
IAM, FRAM_UNI(6) | FRAM | 3 V | 0.27 | 0.58 | 1.0 | 1.53 | 1.9 | 2.2 | mA | ||||||
IAM,0%(7) | FRAM 0% cache hit ratio |
3 V | 0.42 | 0.73 | 1.2 | 1.6 | 2.2 | 2.8 | 2.3 | 2.9 | 2.8 | 3.6 | 3.45 | 4.3 | mA |
IAM,50%(7) (4) | FRAM 50% cache hit ratio |
3 V | 0.31 | 0.73 | 1.3 | 1.75 | 2.1 | 2.5 | mA | ||||||
IAM,66%(7) (4) | FRAM 66% cache hit ratio |
3 V | 0.27 | 0.58 | 1.0 | 1.55 | 1.9 | 2.2 | mA | ||||||
IAM,75%(7) (4) | FRAM 75% cache hit ratio |
3 V | 0.25 | 0.5 | 0.82 | 1.3 | 1.6 | 1.8 | mA | ||||||
IAM,100%(7) (4) | FRAM 100% cache hit ratio |
3 V | 0.2 | 0.43 | 0.3 | 0.55 | 0.42 | 0.8 | 0.73 | 1.15 | 0.88 | 1.3 | 1.0 | 1.5 | mA |
IAM, RAM(4) (8) | RAM | 3 V | 0.2 | 0.4 | 0.35 | 0.55 | 0.55 | 0.75 | 1.0 | 1.25 | 1.20 | 1.45 | 1.45 | 1.75 | mA |
PARAMETER | VCC | –40°C | 25°C | 60°C | 85°C | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|---|---|
TYP | MAX | TYP | MAX | TYP | MAX | TYP | MAX | ||||
ILPM0,1MHz | Low-power mode 0 (3) (12) | 2 V, 3 V |
166 | 175 | 190 | 225 | µA | ||||
LPM0,8MHz | Low-power mode 0 (4) (12) | 2 V, 3 V |
170 | 177 | 244 | 195 | 225 | 360 | µA | ||
LPM0,24MHz | Low-power mode 0 (5) (12) | 2 V, 3 V |
274 | 285 | 340 | 315 | 340 | 455 | µA | ||
ILPM2 | Low-power mode 2 (6) (13) | 2 V, 3 V |
56 | 61 | 80 | 75 | 110 | 210 | µA | ||
ILPM3,XT1LF | Low-power mode 3, crystal mode (7) (13) | 2 V, 3 V |
3.4 | 6.4 | 15 | 18 | 48 | 150 | µA | ||
ILPM3,VLO | Low-power mode 3, VLO mode (8) (13) | 2 V, 3 V |
3.3 | 6.3 | 15 | 18 | 48 | 150 | µA | ||
ILPM4 | Low-power mode 4 (9) (13) | 2 V, 3 V |
2.9 | 5.9 | 15 | 18 | 48 | 150 | µA | ||
ILPM3.5 | Low-power mode 3.5 (10) | 2 V, 3 V |
1.3 | 1.5 | 2.2 | 1.9 | 2.8 | 5.0 | µA | ||
ILPM4.5 | Low-power mode 4.5 (11) | 2 V, 3 V |
0.3 | 0.32 | 0.66 | 0.38 | 0.57 | 2.55 | µA |
PARAMETER | PACKAGE | VALUE(1) | UNIT | |
---|---|---|---|---|
θJA | Junction-to-ambient thermal resistance, still air(2) | TSSOP-24 (PW) | 78.8 | °C/W |
θJC(TOP) | Junction-to-case (top) thermal resistance(3) | 19.4 | °C/W | |
θJB | Junction-to-board thermal resistance(5) | 36.7 | °C/W | |
ΨJB | Junction-to-board thermal characterization parameter | 36.2 | °C/W | |
ΨJT | Junction-to-top thermal characterization parameter | 0.5 | °C/W | |
θJC(BOTTOM) | Junction-to-case (bottom) thermal resistance(4) | N/A | °C/W | |
θJA | Junction-to-ambient thermal resistance, still air(2) | QFN-24 (RGE) | 42.1 | °C/W |
θJC(TOP) | Junction-to-case (top) thermal resistance(3) | 38.8 | °C/W | |
θJB | Junction-to-board thermal resistance(5) | 18.1 | °C/W | |
ΨJB | Junction-to-board thermal characterization parameter | 18.0 | °C/W | |
ΨJT | Junction-to-top thermal characterization parameter | 0.6 | °C/W | |
θJC(BOTTOM) | Junction-to-case (bottom) thermal resistance(4) | 2.8 | °C/W | |
θJA | Junction-to-ambient thermal resistance, still air(2) | SOIC-38 (DA) | 74.5 | °C/W |
θJC(TOP) | Junction-to-case (top) thermal resistance(3) | 22.0 | °C/W | |
θJB | Junction-to-board thermal resistance(5) | 40.7 | °C/W | |
ΨJB | Junction-to-board thermal characterization parameter | 40.3 | °C/W | |
ΨJT | Junction-to-top thermal characterization parameter | 0.9 | °C/W | |
θJC(BOTTOM) | Junction-to-case (bottom) thermal resistance(4) | N/A | °C/W | |
θJA | Junction-to-ambient thermal resistance, still air(2) | QFN-40 (RHA) | 37.8 | °C/W |
θJC(TOP) | Junction-to-case (top) thermal resistance(3) | 27.4 | °C/W | |
θJB | Junction-to-board thermal resistance(5) | 12.6 | °C/W | |
ΨJB | Junction-to-board thermal characterization parameter | 12.6 | °C/W | |
ΨJT | Junction-to-top thermal characterization parameter | 0.4 | °C/W | |
θJC(BOTTOM) | Junction-to-case (bottom) thermal resistance(4) | 3.6 | °C/W |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VIT+ | Positive-going input threshold voltage | 2 V | 0.80 | 1.40 | V | ||
3 V | 1.50 | 2.10 | |||||
VIT– | Negative-going input threshold voltage | 2 V | 0.45 | 1.10 | V | ||
3 V | 0.75 | 1.65 | |||||
Vhys | Input voltage hysteresis (VIT+ – VIT–) | 2 V | 0.25 | 0.8 | V | ||
3 V | 0.30 | 1.0 | |||||
RPull | Pullup or pulldown resistor | For pullup: VIN = VSS
For pulldown: VIN = VCC |
20 | 35 | 50 | kΩ | |
CI | Input capacitance | VIN = VSS or VCC | 5 | pF |
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
t(int) | External interrupt timing (2) | External trigger pulse duration to set interrupt flag | 2 V, 3 V | 20 | ns |
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
Ilkg(Px.x) | High-impedance leakage current | (1) (2) | 2 V, 3 V | –50 | 50 | nA |
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
VOH | High-level output voltage | I(OHmax) = –1 mA (1) | 2 V | VCC – 0.25 | VCC | V |
I(OHmax) = –3 mA (2) | VCC – 0.60 | VCC | ||||
I(OHmax) = –2 mA (1) | 3 V | VCC – 0.25 | VCC | |||
I(OHmax) = –6 mA (2) | VCC – 0.60 | VCC | ||||
VOL | Low-level output voltage | I(OLmax) = 1 mA (1) | 2 V | VSS | VSS + 0.25 | V |
I(OLmax) = 3 mA (2) | VSS | VSS + 0.60 | ||||
I(OLmax) = 2 mA (1) | 3 V | VSS | VSS + 0.25 | |||
I(OLmax) = 6 mA (2) | VSS | VSS + 0.60 |
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
fPx.y | Port output frequency (with load) | Px.y (1) (2) | 2 V | 16 | MHz | |
3 V | 24 | |||||
fPort_CLK | Clock output frequency | ACLK, SMCLK, or MCLK at configured output port, CL = 20 pF, no DC loading (2) |
2 V | 16 | MHz | |
3 V | 24 |
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC = 2.0 V | Measured at Px.y |
VCC = 3.0 V | Measured at Px.y |
VCC = 2.0 V | Measured at Px.y |
VCC = 3.0 V | Measured at Px.y |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
ΔIVCC.LF | Additional current consumption XT1 LF mode from lowest drive setting | fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {1}, CL,eff = 9 pF, TA = 25°C, |
3 V | 60 | nA | ||
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {2}, TA = 25°C, CL,eff = 9 pF |
3 V | 90 | |||||
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {3}, TA = 25°C, CL,eff = 12 pF |
3 V | 140 | |||||
fXT1,LF0 | XT1 oscillator crystal frequency, LF mode | XTS = 0, XT1BYPASS = 0 | 32768 | Hz | |||
fXT1,LF,SW | XT1 oscillator logic-level square-wave input frequency, LF mode | XTS = 0, XT1BYPASS = 1 (6) (7) | 10 | 32.768 | 50 | kHz | |
OALF | Oscillation allowance for LF crystals (8) | XTS = 0, XT1BYPASS = 0, XT1DRIVE = {0}, fXT1,LF = 32768 Hz, CL,eff = 6 pF |
210 | kΩ | |||
XTS = 0, XT1BYPASS = 0, XT1DRIVE = {3}, fXT1,LF = 32768 Hz, CL,eff = 12 pF |
300 | ||||||
Duty cycle, LF mode | XTS = 0, Measured at ACLK, fXT1,LF = 32768 Hz |
30% | 70% | ||||
fFault,LF | Oscillator fault frequency, LF mode (4) | XTS = 0 (3) | 10 | 10000 | Hz | ||
tSTART,LF | Start-up time, LF mode (9) | fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {0}, TA = 25°C, CL,eff = 6 pF |
3 V | 1000 | ms | ||
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {3}, TA = 25°C, CL,eff = 12 pF |
1000 | ||||||
CL,eff | Integrated effective load capacitance, LF mode (1) (2) | XTS = 0 | 1 | pF |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
IVCC,HF | XT1 oscillator crystal current HF mode | fOSC = 4 MHz, XTS = 1, XOSCOFF = 0, XT1BYPASS = 0, XT1DRIVE = {0}, TA = 25°C, CL,eff = 16 pF |
3 V | 175 | µA | ||
fOSC = 8 MHz, XTS = 1, XOSCOFF = 0, XT1BYPASS = 0, XT1DRIVE = {1}, TA = 25°C, CL,eff = 16 pF |
300 | ||||||
fOSC = 16 MHz, XTS = 1, XOSCOFF = 0, XT1BYPASS = 0, XT1DRIVE = {2}, TA = 25°C, CL,eff = 16 pF |
350 | ||||||
fOSC = 24 MHz, XTS = 1, XOSCOFF = 0, XT1BYPASS = 0, XT1DRIVE = {3}, TA = 25°C, CL,eff = 16 pF |
550 | ||||||
fXT1,HF0 | XT1 oscillator crystal frequency, HF mode 0 | XTS = 1, XT1BYPASS = 0, XT1DRIVE = {0} (7) |
4 | 6 | MHz | ||
fXT1,HF1 | XT1 oscillator crystal frequency, HF mode 1 | XTS = 1, XT1BYPASS = 0, XT1DRIVE = {1} (7) |
6 | 10 | MHz | ||
fXT1,HF2 | XT1 oscillator crystal frequency, HF mode 2 | XTS = 1, XT1BYPASS = 0, XT1DRIVE = {2} (7) |
10 | 16 | MHz | ||
fXT1,HF3 | XT1 oscillator crystal frequency, HF mode 3 | XTS = 1, XT1BYPASS = 0, XT1DRIVE = {3} (7) |
16 | 24 | MHz | ||
fXT1,HF,SW | XT1 oscillator logic-level square-wave input frequency, HF mode | XTS = 1, XT1BYPASS = 1 (6) (7) |
1 | 24 | MHz | ||
OAHF | Oscillation allowance for HF crystals (8) | XTS = 1, XT1BYPASS = 0, XT1DRIVE = {0}, fXT1,HF = 4 MHz, CL,eff = 16 pF |
450 | Ω | |||
XTS = 1, XT1BYPASS = 0, XT1DRIVE = {1}, fXT1,HF = 8 MHz, CL,eff = 16 pF |
320 | ||||||
XTS = 1, XT1BYPASS = 0, XT1DRIVE = {2}, fXT1,HF = 16 MHz, CL,eff = 16 pF |
200 | ||||||
XTS = 1, XT1BYPASS = 0, XT1DRIVE = {3}, fXT1,HF = 24 MHz, CL,eff = 16 pF |
200 | ||||||
tSTART,HF | Start-up time, HF mode (9) | fOSC = 4 MHz, XTS = 1, XT1BYPASS = 0, XT1DRIVE = {0}, TA = 25°C, CL,eff = 16 pF |
3 V | 8 | ms | ||
fOSC = 24 MHz, XTS = 1, XT1BYPASS = 0, XT1DRIVE = {3}, TA = 25°C, CL,eff = 16 pF |
2 | ||||||
CL,eff | Integrated effective load capacitance (1) (2) | XTS = 1 | 1 | pF | |||
Duty cycle, HF mode | XTS = 1, Measured at ACLK, fXT1,HF2 = 24 MHz |
40% | 50% | 60% | |||
fFault,HF | Oscillator fault frequency, HF mode (4) | XTS = 1 (3) | 145 | 900 | kHz |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fVLO | VLO frequency | Measured at ACLK | 2 V to 3.6 V | 5 | 8.3 | 13 | kHz |
dfVLO/dT | VLO frequency temperature drift | Measured at ACLK (1) | 2 V to 3.6 V | 0.5 | %/°C | ||
dfVLO/dVCC | VLO frequency supply voltage drift | Measured at ACLK (2) | 2 V to 3.6 V | 4 | %/V | ||
fVLO,DC | Duty cycle | Measured at ACLK | 2 V to 3.6 V | 40% | 50% | 60% |
NOTE
In LPM3, the VLO frequency varies by up to ±6% (typical), due to bias current sampling. This frequency variation is not a violation VLO specifications (see Section 5.15).
PARAMETER | TEST CONDITIONS | VCC
TA |
MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fDCO,LO | DCO frequency low, trimmed | Measured at ACLK, DCORSEL = 0 |
2 V to 3.6 V –40°C to 85°C |
5.37 | ±3.5% | MHz | |
2 V to 3.6 V 0°C to 50°C |
5.37 | ±2.0% | |||||
Measured at ACLK, DCORSEL = 1 |
2 V to 3.6 V –40°C to 85°C |
16.2 | ±3.5% | ||||
2 V to 3.6 V 0°C to 50°C |
16.2 | ±2.0% | |||||
fDCO,MID | DCO frequency mid, trimmed | Measured at ACLK, DCORSEL = 0 |
2 V to 3.6 V –40°C to 85°C |
6.67 | ±3.5% | MHz | |
2 V to 3.6 V 0°C to 50°C |
6.67 | ±2.0% | |||||
Measured at ACLK, DCORSEL = 1 |
2 V to 3.6 V –40°C to 85°C |
20 | ±3.5% | ||||
2 V to 3.6 V 0°C to 50°C |
20 | ±2.0% | |||||
fDCO,HI | DCO frequency high, trimmed | Measured at ACLK, DCORSEL = 0 |
2 V to 3.6 V –40°C to 85°C |
8 | ±3.5% | MHz | |
2 V to 3.6 V 0°C to 50°C |
8 | ±2.0% | |||||
Measured at ACLK, DCORSEL = 1 |
2 V to 3.6 V –40°C to 85°C |
23.8 | ±3.5% | ||||
2 V to 3.6 V 0°C to 50°C |
23.8 | ±2.0% | |||||
fDCO,DC | Duty cycle | Measured at ACLK, divide by 1, No external divide, all DCO settings |
2 V to 3.6 V –40°C to 85°C |
40% | 50% | 60% |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
IMODOSC | Current consumption | Enabled | 2 V to 3.6 V | 44 | 80 | µA | |
fMODOSC | MODOSC frequency | 2 V to 3.6 V | 4.5 | 5.0 | 5.5 | MHz | |
fMODOSC,DC | Duty cycle | Measured at ACLK, divide by 1 | 2 V to 3.6 V | 40% | 50% | 60% |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VCORE(AM) | Core voltage, active mode | 2 V ≤ DVCC ≤ 3.6 V | 1.5 | V | ||
VCORE(LPM) | Core voltage, low-current mode | 2 V ≤ DVCC ≤ 3.6 V | 1.5 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ISVSH,AM | SVSH current consumption, active mode | VCC = 3.6 V | 5 | µA | ||
ISVSH,LPM | SVSH current consumption, low power modes | VCC = 3.6 V | 0.8 | 1.5 | µA | |
VSVSH- | SVSH on voltage level, falling supply voltage | 1.83 | 1.88 | 1.93 | V | |
VSVSH+ | SVSH off voltage level, rising supply voltage | 1.88 | 1.93 | 1.98 | V | |
tPD,SVSH, AM | SVSH propagation delay, active mode | dVCC/dt = 10 mV/µs | 10 | µs | ||
tPD,SVSH, LPM | SVSH propagation delay, low power modes | dVCC/dt = 1 mV/µs | 30 | µs | ||
ISVSL | SVSL current consumption | 0.3 | 0.5 | µA | ||
VSVSL– | SVSL on voltage level | 1.42 | V | |||
VSVSL+ | SVSL off voltage level | 1.47 | V |
PARAMETER | TEST CONDITIONS | VCC
TA |
MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tWAKE-UP LPM0 | Wake-up time from LPM0 to active mode (1) | 2 V, 3 V –40°C to 85°C |
0.58 | 1 | µs | ||
tWAKE-UP LPM12 | Wake-up time from LPM1, LPM2 to active mode (1) | 2 V, 3 V –40°C to 85°C |
12 | 25 | µs | ||
tWAKE-UP LPM34 | Wake-up time from LPM3 or LPM4 to active mode (1) | 2 V, 3 V –40°C to 85°C |
78 | 120 | µs | ||
tWAKE-UP LPMx.5 | Wake-up time from LPM3.5 or LPM4.5 to active mode (1) | 2 V, 3 V 0°C to 85°C |
310 | 575 | µs | ||
2 V, 3 V –40°C to 85°C |
310 | 1100 | |||||
tWAKE-UP RESET | Wake-up time from RST to active mode (2) | VCC stable |
2 V, 3 V –40°C to 85°C |
230 | 280 | µs | |
tWAKE-UP BOR | Wake-up time from BOR or power-up to active mode | dVCC/dt = 2400 V/s | 2 V, 3 V –40°C to 85°C |
1.6 | ms | ||
tRESET | Pulse duration required at RST/NMI terminal to accept a reset event(3) | 2 V, 3 V –40°C to 85°C |
4 | ns |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fTA | Timer_A input clock frequency | Internal: SMCLK, ACLK External: TACLK Duty cycle = 50% ±10% |
2 V, 3 V | 24 | MHz | ||
tTA,cap | Timer_A capture timing | All capture inputs, Minimum pulse duration required for capture | 2 V, 3 V | 20 | ns |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fTB | Timer_B input clock frequency | Internal: SMCLK, ACLK External: TBCLK Duty cycle = 50% ±10% |
2 V, 3 V | 24 | MHz | ||
tTB,cap | Timer_B capture timing | All capture inputs, Minimum pulse duration required for capture | 2 V, 3 V | 20 | ns |
PARAMETER | CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
feUSCI | eUSCI input clock frequency | Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ±10% |
fSYSTEM | MHz | |||
fBITCLK | BITCLK clock frequency (equals baud rate in MBaud) |
5 | MHz |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tt | UART receive deglitch time(1) | UCGLITx = 0 | 2 V, 3 V | 5 | 15 | 20 | ns |
UCGLITx = 1 | 20 | 45 | 60 | ||||
UCGLITx = 2 | 35 | 80 | 120 | ||||
UCGLITx = 3 | 50 | 110 | 180 |
PARAMETER | CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
feUSCI | eUSCI input clock frequency | Internal: SMCLK, ACLK Duty cycle = 50% ±10% |
fSYSTEM | MHz |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tSTE,LEAD | STE lead time, STE active to clock | UCSTEM = 0, UCMODEx = 01 or 10 |
2 V, 3 V | 1 | UCxCLK cycles | ||
UCSTEM = 1, UCMODEx = 01 or 10 |
2 V, 3 V | 1 | |||||
tSTE,LAG | STE lag time, Last clock to STE inactive | UCSTEM = 0, UCMODEx = 01 or 10 |
2 V, 3 V | 1 | UCxCLK cycles | ||
UCSTEM = 1, UCMODEx = 01 or 10 |
2 V, 3 V | 1 | |||||
tSTE,ACC | STE access time, STE active to SIMO data out | UCSTEM = 0, UCMODEx = 01 or 10 |
2 V, 3 V | 55 | ns | ||
UCSTEM = 1, UCMODEx = 01 or 10 |
2 V, 3 V | 35 | |||||
tSTE,DIS | STE disable time, STE inactive to SIMO high impedance | UCSTEM = 0, UCMODEx = 01 or 10 |
2 V, 3 V | 40 | ns | ||
UCSTEM = 1, UCMODEx = 01 or 10 |
2 V, 3 V | 30 | |||||
tSU,MI | SOMI input data setup time | 2 V | 35 | ns | |||
3 V | 35 | ||||||
tHD,MI | SOMI input data hold time | 2 V | 0 | ns | |||
3 V | 0 | ||||||
tVALID,MO | SIMO output data valid time (2) | UCLK edge to SIMO valid, CL = 20 pF |
2 V | 30 | ns | ||
3 V | 30 | ||||||
tHD,MO | SIMO output data hold time (3) | CL = 20 pF | 2 V | 0 | ns | ||
3 V | 0 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tSTE,LEAD | STE lead time, STE active to clock | 2 V | 7 | ns | |||
3 V | 7 | ||||||
tSTE,LAG | STE lag time, Last clock to STE inactive | 2 V | 0 | ns | |||
3 V | 0 | ||||||
tSTE,ACC | STE access time, STE active to SOMI data out | 2 V | 65 | ns | |||
3 V | 40 | ||||||
tSTE,DIS | STE disable time, STE inactive to SOMI high impedance | 2 V | 40 | ns | |||
3 V | 35 | ||||||
tSU,SI | SIMO input data setup time | 2 V | 2 | ns | |||
3 V | 2 | ||||||
tHD,SI | SIMO input data hold time | 2 V | 5 | ns | |||
3 V | 5 | ||||||
tVALID,SO | SOMI output data valid time (2) | UCLK edge to SOMI valid, CL = 20 pF |
2 V | 30 | ns | ||
3 V | 30 | ||||||
tHD,SO | SOMI output data hold time (3) | CL = 20 pF | 2 V | 4 | ns | ||
3 V | 4 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
feUSCI | eUSCI input clock frequency | Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ±10% |
fSYSTEM | MHz | |||
fSCL | SCL clock frequency | 2 V, 3 V | 0 | 400 | kHz | ||
tHD,STA | Hold time (repeated) START | fSCL = 100 kHz | 2 V, 3 V | 4.0 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tSU,STA | Setup time for a repeated START | fSCL = 100 kHz | 2 V, 3 V | 4.7 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tHD,DAT | Data hold time | 2 V, 3 V | 0 | ns | |||
tSU,DAT | Data setup time | 2 V, 3 V | 250 | ns | |||
tSU,STO | Setup time for STOP | fSCL = 100 kHz | 2 V, 3 V | 4.0 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tSP | Pulse duration of spikes suppressed by input filter | UCGLITx = 0 | 2 V, 3 V | 50 | 600 | ns | |
UCGLITx = 1 | 25 | 300 | |||||
UCGLITx = 2 | 12.5 | 150 | |||||
UCGLITx = 3 | 6.25 | 75 | |||||
tTIMEOUT | Clock low time-out | UCCLTOx = 1 | 2 V, 3 V | 27 | ms | ||
UCCLTOx = 2 | 30 | ||||||
UCCLTOx = 3 | 33 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
AVCC | Analog supply voltage | AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V |
2.0 | 3.6 | V | ||
V(Ax) | Analog input voltage range | All ADC10 pins | 0 | AVCC | V | ||
IADC10_A | Operating supply current into AVCC terminal, reference current not included | fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0 |
2 V | 90 | 140 | µA | |
3 V | 100 | 160 | |||||
CI | Input capacitance | Only one terminal Ax can be selected at one time from the pad to the ADC10_A capacitor array including wiring and pad | 2.2 V | 6 | 8 | pF | |
RI | Input MUX ON resistance | AVCC ≥ 2 V, 0 V ≤ VAx ≤ AVCC | 36 | kΩ |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fADC10CLK | For specified performance of ADC10 linearity parameters | 2 V to 3.6 V | 0.45 | 5 | 5.5 | MHz | |
fADC10OSC | Internal ADC10 oscillator (MODOSC) | ADC10DIV = 0, fADC10CLK = fADC10OSC | 2 V to 3.6 V | 4.5 | 4.5 | 5.5 | MHz |
tCONVERT | Conversion time | REFON = 0, Internal oscillator, 12 ADC10CLK cycles, 10-bit mode, fADC10OSC = 4.5 MHz to 5.5 MHz |
2 V to 3.6 V | 2.18 | 2.67 | µs | |
External fADC10CLK from ACLK, MCLK, or SMCLK, ADC10SSEL ≠ 0 | 2 V to 3.6 V | (1) | |||||
tADC10ON | Turnon settling time of the ADC | The error in a conversion started after tADC10ON is less than ±0.5 LSB, Reference and input signal already settled |
100 | ns | |||
tSample | Sampling time | RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF, Approximately eight Tau (τ) are required to get an error of less than ±0.5 LSB |
2 V | 1.5 | µs | ||
3 V | 2.0 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
EI | Integral linearity error | 1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V | 2 V to 3.6 V | –1.4 | 1.4 | LSB | |
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC | –1.1 | 1.1 | |||||
ED | Differential linearity error | (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–) | 2 V to 3.6 V | –1 | 1 | LSB | |
EO | Offset error | (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–) | 2 V to 3.6 V | –6.5 | 6.5 | mV | |
EG | Gain error, external reference | (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–) | 2 V to 3.6 V | –1.2 | 1.2 | LSB | |
Gain error, internal reference (1) | –4% | 4% | |||||
ET | Total unadjusted error, external reference | (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–) | 2 V to 3.6 V | –2 | 2 | LSB | |
Total unadjusted error, internal reference (1) | –4% | 4% |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VeREF+ | Positive external reference voltage input | VeREF+ > VeREF– (2) | 1.4 | AVCC | V | ||
VeREF– | Negative external reference voltage input | VeREF+ > VeREF– (3) | 0 | 1.2 | V | ||
(VeREF+ – VREF–/VeREF–) |
Differential external reference voltage input | VeREF+ > VeREF– (4) | 1.4 | AVCC | V | ||
IVeREF+, IVeREF– |
Static input current | 1.4 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V, fADC10CLK = 5 MHz, ADC10SHTx = 1h, Conversion rate 200 ksps |
2.2 V, 3 V | –6 | 6 | µA | |
1.4 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V, fADC10CLK = 5 MHz, ADC10SHTx = 8h, Conversion rate 20 ksps |
2.2 V, 3 V | –1 | 1 | ||||
CVREF+, CVREF- |
Capacitance at VREF+ or VREF- terminal(5) | 10 | µF |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VREF+ | Positive built-in reference voltage output | REFVSEL = {2} for 2.5 V, REFON = 1 | 3 V | 2.4 | 2.5 | 2.6 | V |
REFVSEL = {1} for 2 V, REFON = 1 | 3 V | 1.92 | 2.0 | 2.08 | |||
REFVSEL = {0} for 1.5 V, REFON = 1 | 3 V | 1.44 | 1.5 | 1.56 | |||
AVCC(min) | AVCC minimum voltage, Positive built-in reference active | REFVSEL = {0} for 1.5 V | 2.0 | V | |||
REFVSEL = {1} for 2 V | 2.2 | ||||||
REFVSEL = {2} for 2.5 V | 2.7 | ||||||
IREF+ | Operating supply current into AVCC terminal (1) | fADC10CLK = 5 MHz, REFON = 1, REFBURST = 0 |
3 V | 33 | 45 | µA | |
TREF+ | Temperature coefficient of built-in reference | REFVSEL = (0, 1, 2}, REFON = 1 | ±35 | ppm/ °C | |||
PSRR_DC | Power supply rejection ratio (DC) | AVCC = AVCC (min) - AVCC(max), TA = 25°C, REFON = 1, REFVSEL = (0} for 1.5 V |
1600 | µV/V | |||
AVCC = AVCC (min) - AVCC(max), TA = 25°C, REFON = 1, REFVSEL = (1} for 2 V |
1900 | ||||||
AVCC = AVCC (min) - AVCC(max), TA = 25°C, REFON = 1, REFVSEL = (2} for 2.5 V |
3600 | ||||||
tSETTLE | Settling time of reference voltage (2) | AVCC = AVCC (min) - AVCC(max), REFVSEL = (0, 1, 2}, REFON = 0 → 1 |
30 | µs |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VSENSOR | See (1) | ADC10ON = 1, INCH = 0Ah, TA = 0°C |
2 V, 3 V | 790 | mV | ||
TCSENSOR | ADC10ON = 1, INCH = 0Ah | 2 V, 3 V | 2.55 | mV/°C | |||
tSENSOR(sample) | Sample time required if channel 10 is selected (2) | ADC10ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB |
2 V | 30 | µs | ||
3 V | 30 | ||||||
VMID | AVCC divider at channel 11 | ADC10ON = 1, INCH = 0Bh, VMID is ~0.5 × VAVCC |
2 V | 0.97 | 1.0 | 1.03 | V |
3 V | 1.46 | 1.5 | 1.54 | ||||
tVMID(sample) | Sample time required if channel 11 is selected (3) | ADC10ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB |
2 V, 3 V | 1000 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tpd | Propagation delay, AVCC = 2 V to 3.6 V |
Overdrive = 10 mV, VIN- = (VIN+ – 400 mV) to (VIN+ + 10 mV) |
50 | 100 | 200 | ns |
Overdrive = 100 mV, VIN- = (VIN+ – 400 mV) to (VIN+ + 100 mV) |
80 | |||||
Overdrive = 250 mV, (VIN+ – 400 mV) to (VIN+ + 250 mV) |
50 | |||||
tfilter | Filter timer added to the propagation delay of the comparator | CDF = 1, CDFDLY = 00 | 0.3 | 0.5 | 0.9 | µs |
CDF = 1, CDFDLY = 01 | 0.5 | 0.9 | 1.5 | |||
CDF = 1, CDFDLY = 10 | 0.9 | 1.6 | 2.8 | |||
CDF = 1, CDFDLY = 11 | 1.6 | 3.0 | 5.5 | |||
Voffset | Input offset | AVCC = 2 V to 3.6 V | –20 | 20 | mV | |
Vic | Common mode input range | AVCC = 2 V to 3.6 V | 0 | AVCC - 1 | V | |
Icomp(AVCC) | Comparator only | CDON = 1, AVCC = 2 V to 3.6 V | 29 | 34 | µA | |
Iref(AVCC) | Reference buffer and R‑ladder | CDREFLx = 01, AVCC = 2 V to 3.6 V | 20 | 24 | µA | |
tenable,comp | Comparator enable time | CDON = 0 to CDON = 1, AVCC = 2 V to 3.6 V |
1.1 | 2.0 | µs | |
tenable,rladder | Resistor ladder enable time | CDON = 0 to CDON = 1, AVCC = 2 V to 3.6 V |
1.1 | 2.0 | µs | |
VCB_REF | Reference voltage for a tap | VIN = voltage input to the R-ladder, n = 0 to 31 |
VIN × (n + 0.5) / 32 | VIN × (n + 1) / 32 |
VIN × (n + 1.5) / 32 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DVCC(WRITE) | Write supply voltage | 2.0 | 3.6 | V | ||
tWRITE | Word or byte write time | 120 | ns | |||
tACCESS | Read access time (1) | 60 | ns | |||
tPRECHARGE | Precharge time (1) | 60 | ns | |||
tCYCLE | Cycle time, read or write operation (1) | 120 | ns | |||
Read and write endurance | 1015 | cycles | ||||
tRetention | Data retention duration | TJ = 25°C | 100 | years | ||
TJ = 70°C | 40 | |||||
TJ = 85°C | 10 |
PARAMETER | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fSBW | Spy-Bi-Wire input frequency | 2 V, 3 V | 0 | 20 | MHz | |
tSBW,Low | Spy-Bi-Wire low clock pulse duration | 2 V, 3 V | 0.025 | 15 | µs | |
tSBW, En | Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) | 2 V, 3 V | 1 | µs | ||
tSBW,Rst | Spy-Bi-Wire return to normal operation time | 19 | 35 | µs | ||
fTCK | TCK input frequency, 4-wire JTAG (2) | 2 V | 0 | 5 | MHz | |
3 V | 0 | 10 | ||||
Rinternal | Internal pulldown resistance on TEST | 2 V, 3 V | 20 | 35 | 50 | kΩ |