SLAS639L July   2011  – December 2017 MSP430FR5730 , MSP430FR5731 , MSP430FR5732 , MSP430FR5733 , MSP430FR5734 , MSP430FR5735 , MSP430FR5736 , MSP430FR5737 , MSP430FR5738 , MSP430FR5739

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram - RHA Package - MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, MSP430FR5739
    2. 4.2 Pin Diagram - DA Package - MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, MSP430FR5739
    3. 4.3 Pin Diagram - RGE Package - MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, MSP430FR5738
    4. 4.4 Pin Diagram - YQD Package - MSP430FR5738
    5. 4.5 Pin Diagram - PW Package - MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, MSP430FR5738
    6. 4.6 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
    8. 5.8  Inputs - Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
    10. 5.10 Outputs - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
    11. 5.11 Output Frequency - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
    12. 5.12 Typical Characteristics - Outputs
    13. 5.13 Crystal Oscillator, XT1, Low-Frequency (LF) Mode
    14. 5.14 Crystal Oscillator, XT1, High-Frequency (HF) Mode
    15. 5.15 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    16. 5.16 DCO Frequencies
    17. 5.17 MODOSC
    18. 5.18 PMM, Core Voltage
    19. 5.19 PMM, SVS, BOR
    20. 5.20 Wake-up Times From Low-Power Modes
    21. 5.21 Timer_A
    22. 5.22 Timer_B
    23. 5.23 eUSCI (UART Mode) Clock Frequency
    24. 5.24 eUSCI (UART Mode)
    25. 5.25 eUSCI (SPI Master Mode) Clock Frequency
    26. 5.26 eUSCI (SPI Master Mode)
    27. 5.27 eUSCI (SPI Slave Mode)
    28. 5.28 eUSCI (I2C Mode)
    29. 5.29 10-Bit ADC, Power Supply and Input Range Conditions
    30. 5.30 10-Bit ADC, Timing Parameters
    31. 5.31 10-Bit ADC, Linearity Parameters
    32. 5.32 REF, External Reference
    33. 5.33 REF, Built-In Reference
    34. 5.34 REF, Temperature Sensor and Built-In VMID
    35. 5.35 Comparator_D
    36. 5.36 FRAM
    37. 5.37 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Functional Block Diagrams
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  FRAM
    9. 6.9  Memory Protection Unit (MPU)
    10. 6.10 Peripherals
      1. 6.10.1  Digital I/O
      2. 6.10.2  Oscillator and Clock System (CS)
      3. 6.10.3  Power-Management Module (PMM)
      4. 6.10.4  Hardware Multiplier (MPY)
      5. 6.10.5  Real-Time Clock (RTC_B)
      6. 6.10.6  Watchdog Timer (WDT_A)
      7. 6.10.7  System Module (SYS)
      8. 6.10.8  DMA Controller
      9. 6.10.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.10.10 TA0, TA1
      11. 6.10.11 TB0, TB1, TB2
      12. 6.10.12 ADC10_B
      13. 6.10.13 Comparator_D
      14. 6.10.14 CRC16
      15. 6.10.15 Shared Reference (REF)
      16. 6.10.16 Embedded Emulation Module (EEM)
      17. 6.10.17 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      6. 6.11.6  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P2 (P2.7) Input/Output With Schmitt Trigger
      8. 6.11.8  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      9. 6.11.9  Port P3 (P3.4 to P3.6) Input/Output With Schmitt Trigger
      10. 6.11.10 Port Port P3 (P3.7) Input/Output With Schmitt Trigger
      11. 6.11.11 Port Port P4 (P4.0) Input/Output With Schmitt Trigger
      12. 6.11.12 Port Port P4 (P4.1) Input/Output With Schmitt Trigger
      13. 6.11.13 Port Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
      14. 6.11.14 Port Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
  7. 7Device and Documentation Support
    1. 7.1  Getting Started
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Terminal Configuration and Functions

4.1 Pin Diagram – RHA Package –
MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, MSP430FR5739

Figure 4-1 shows the pin diagram for the MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, and MSP430FR5739 devices in the 40-pin RHA package.

MSP430FR5739 MSP430FR5738 MSP430FR5737 MSP430FR5736 MSP430FR5735 MSP430FR5734 MSP430FR5733 MSP430FR5732 MSP430FR5731 MSP430FR5730 slas639-pin_fr5739_37_35_33_31_29_27_25_23_21_rha.gif
* Not available on MSP430FR5737, MSP430FR5733

NOTE:

Exposed thermal pad connection to VSS recommended.
Figure 4-1 40-Pin RHA Package (Top View)

4.2 Pin Diagram – DA Package –
MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, MSP430FR5739

Figure 4-2 shows the pin diagram for the MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, and MSP430FR5739 devices in the 38-pin DA package.

MSP430FR5739 MSP430FR5738 MSP430FR5737 MSP430FR5736 MSP430FR5735 MSP430FR5734 MSP430FR5733 MSP430FR5732 MSP430FR5731 MSP430FR5730 slas639-pin_fr5739_37_35_33_31_29_27_25_23_21_da.gif
* Not available on MSP430FR5737, MSP430FR5733
Figure 4-2 38-Pin DA Package (Top View)

4.3 Pin Diagram – RGE Package –
MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, MSP430FR5738

Figure 4-3 shows the pin diagram for the MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, and MSP430FR5738 devices in the 24-pin RGE package.

MSP430FR5739 MSP430FR5738 MSP430FR5737 MSP430FR5736 MSP430FR5735 MSP430FR5734 MSP430FR5733 MSP430FR5732 MSP430FR5731 MSP430FR5730 slas639-pin_fr5738_36_34_32_30_28_26_24_22_20_rge.gif
* Not available on MSP430FR5736, MSP430FR5732

NOTE:

Exposed thermal pad connection to VSS recommended.
Figure 4-3 24-Pin RGE Package (Top View)

4.4 Pin Diagram – YQD Package – MSP430FR5738

Figure 4-4 shows the pin diagram for the MSP430FR5738 device in the 24-pin YQD package,

MSP430FR5739 MSP430FR5738 MSP430FR5737 MSP430FR5736 MSP430FR5735 MSP430FR5734 MSP430FR5733 MSP430FR5732 MSP430FR5731 MSP430FR5730 slas639-pin_dsbga_new_coord.gif Figure 4-4 24-Pin YQD Package

4.5 Pin Diagram – PW Package –
MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, MSP430FR5738

Figure 4-5 shows the pin diagram for the MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, and MSP430FR5738 devices in the 28-pin PW package.

MSP430FR5739 MSP430FR5738 MSP430FR5737 MSP430FR5736 MSP430FR5735 MSP430FR5734 MSP430FR5733 MSP430FR5732 MSP430FR5731 MSP430FR5730 slas639-pin_fr5738_36_34_32_30_28_26_24_22_20_pw.gif
* Not available on MSP430FR5736, MSP430FR5732
Figure 4-5 28-Pin PW Package (Top View)

4.6 Signal Descriptions

Table 4-1 describes the signals for all device variants and packages.

Table 4-1 Signal Descriptions

TERMINAL I/O (1) DESCRIPTION
NAME NO.
RHA RGE DA PW YQD
P1.0/TA0.1/DMAE0/ RTCCLK/A0/CD0/VeREF- 1 1 5 5 C2 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA0 CCR1 capture: CCI1A input, compare: Out1
External DMA trigger
RTC clock calibration output
Analog input A0 – ADC (not available on devices without ADC)
Comparator_D input CD0
External applied reference voltage (not available on devices without ADC)
P1.1/TA0.2/TA1CLK/ CDOUT/A1/CD1/VeREF+ 2 2 6 6 D1 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA0 CCR2 capture: CCI2A input, compare: Out2
TA1 input clock
Comparator_D output
Analog input A1 – ADC (not available on devices without ADC)
Comparator_D input CD1
Input for an external reference voltage to the ADC (not available on devices without ADC)
P1.2/TA1.1/TA0CLK/ CDOUT/A2/CD2 3 3 7 7 C1 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA1 CCR1 capture: CCI1A input, compare: Out1
TA0 input clock
Comparator_D output
Analog input A2 – ADC (not available on devices without ADC)
Comparator_D input CD2
P3.0/A12/CD12 4 N/A 8 N/A N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD)
Analog input A12 – ADC (not available on devices without ADC or package options PW, RGE, YQD)
Comparator_D input CD12 (not available on package options PW, RGE, YQD)
P3.1/A13/CD13 5 N/A 9 N/A N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD)
Analog input A13 – ADC (not available on devices without ADC or package options PW, RGE, YQD)
Comparator_D input CD13 (not available on package options PW, RGE, YQD)
P3.2/A14/CD14 6 N/A 10 N/A N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD)
Analog input A14 – ADC (not available on devices without ADC or package options PW, RGE, YQD)
Comparator_D input CD14 (not available on package options PW, RGE, YQD)
P3.3/A15/CD15 7 N/A 11 N/A N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD)
Analog input A15 – ADC (not available on devices without ADC or package options PW, RGE, YQD)
Comparator_D input CD15 (not available on package options PW, RGE, YQD)
P1.3/TA1.2/UCB0STE/ A3/CD3 8 4 12 8 B1 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA1 CCR2 capture: CCI2A input, compare: Out2
Slave transmit enable – eUSCI_B0 SPI mode
Analog input A3 – ADC (not available on devices without ADC)
Comparator_D input CD3
P1.4/TB0.1/UCA0STE/ A4/CD4 9 5 13 9 B2 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB0 CCR1 capture: CCI1A input, compare: Out1
Slave transmit enable – eUSCI_A0 SPI mode
Analog input A4 – ADC (not available on devices without ADC)
Comparator_D input CD4
P1.5/TB0.2/UCA0CLK/ A5/CD5 10 6 14 10 A1 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB0 CCR2 capture: CCI2A input, compare: Out2
Clock signal input – eUSCI_A0 SPI slave mode,
Clock signal output – eUSCI_A0 SPI master mode
Analog input A5 – ADC (not available on devices without ADC)
Comparator_D input CD5
PJ.0/TDO/TB0OUTH/ SMCLK/CD6 (4) 11 7 15 11 C3 I/O General-purpose digital I/O
Test data output port
Switch all PWM outputs high impedance input – TB0
SMCLK output
Comparator_D input CD6
PJ.1/TDI/TCLK/TB1OUTH/ MCLK/CD7 (4) 12 8 16 12 A2 I/O General-purpose digital I/O
Test data input or test clock input
Switch all PWM outputs high impedance input – TB1 (not available on devices without TB1)
MCLK output
Comparator_D input CD7
PJ.2/TMS/TB2OUTH/ ACLK/CD8 (4) 13 9 17 13 B3 I/O General-purpose digital I/O
Test mode select
Switch all PWM outputs high impedance input – TB2 (not available on devices without TB2)
ACLK output
Comparator_D input CD8
PJ.3/TCK/CD9 (4) 14 10 18 14 A3 I/O General-purpose digital I/O
Test clock
Comparator_D input CD9
P4.0/TB2.0 15 N/A N/A N/A N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD)
TB2 CCR0 capture: CCI0B input, compare: Out0 (not available on devices without TB2 or package options DA, PW, RGE, YQD)
P4.1 16 N/A N/A N/A N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options DA, PW, RGE, YQD)
P2.5/TB0.0/UCA1TXD/ UCA1SIMO 17 N/A 19 15 N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB0 CCR0 capture: CCI0A input, compare: Out0
Transmit data – eUSCI_A1 UART mode, Slave in, master out – eUSCI_A1 SPI mode (not available on devices without UCSI_A1)
P2.6/TB1.0/UCA1RXD/ UCA1SOMI 18 N/A 20 16 N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB1)
Receive data – eUSCI_A1 UART mode, Slave out, master in – eUSCI_A1 SPI mode (not available on devices without UCSI_A1)
TEST/SBWTCK (4) (3) 19 11 21 17 A4 I Test mode pin – enable JTAG pins
Spy-Bi-Wire input clock
RST/NMI/SBWTDIO (4) (3) 20 12 22 18 B4 I/O Reset input active low
Non-maskable interrupt input
Spy-Bi-Wire data input/output
P2.0/TB2.0/UCA0TXD/ UCA0SIMO/TB0CLK/ ACLK(3) 21 13 23 19 A5 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB2 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB2)
Transmit data – eUSCI_A0 UART mode
Slave in, master out – eUSCI_A0 SPI mode
TB0 clock input
ACLK output
P2.1/TB2.1/UCA0RXD/ UCA0SOMI/TB0.0(3) 22 14 24 20 C4 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB2 CCR1 capture: CCI1A input, compare: Out1 (not available on devices without TB2)
Receive data – eUSCI_A0 UART mode
Slave out, master in – eUSCI_A0 SPI mode
TB0 CCR0 capture: CCI0A input, compare: Out0
P2.2/TB2.2/UCB0CLK/ TB1.0 23 15 25 21 B5 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB2 CCR2 capture: CCI2A input, compare: Out2 (not available on devices without TB2)
Clock signal input – eUSCI_B0 SPI slave mode,
Clock signal output – eUSCI_B0 SPI master mode
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB1)
P3.4/TB1.1/TB2CLK/ SMCLK 24 N/A 26 N/A N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD)
TB1 CCR1 capture: CCI1B input, compare: Out1 (not available on devices without TB1)
TB2 clock input (not available on devices without TB2 or package options PW, RGE, YQD)
SMCLK output (not available on package options PW, RGE, YQD)
P3.5/TB1.2/CDOUT 25 N/A 27 N/A N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD)
TB1 CCR2 capture: CCI2B input, compare: Out2 (not available on devices without TB1)
Comparator_D output (not available on package options PW, RGE, YQD)
P3.6/TB2.1/TB1CLK 26 N/A 28 N/A N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD)
TB2 CCR1 capture: CCI1B input, compare: Out1 (not available on devices without TB2)
TB1 clock input (not available on devices without TB1 or package options PW, RGE, YQD)
P3.7/TB2.2 27 N/A 29 N/A N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE, YQD)
TB2 CCR2 capture: CCI2B input, compare: Out2 (not available on devices without TB2 or package options PW, RGE, YQD)
P1.6/TB1.1/UCB0SIMO/ UCB0SDA/TA0.0 28 16 30 22 D5 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB1 CCR1 capture: CCI1A input, compare: Out1 (not available on devices without TB1)
Slave in, master out – eUSCI_B0 SPI mode
I2C data – eUSCI_B0 I2C mode
TA0 CCR0 capture: CCI0A input, compare: Out0
P1.7/TB1.2/UCB0SOMI/ UCB0SCL/TA1.0 29 17 31 23 C5 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB1 CCR2 capture: CCI2A input, compare: Out2 (not available on devices without TB1)
Slave out, master in – eUSCI_B0 SPI mode
I2C clock – eUSCI_B0 I2C mode
TA1 CCR0 capture: CCI0A input, compare: Out0
VCORE (2) 30 18 32 24 E5 Regulated core power supply (internal use only, no external current loading)
DVSS 31 19 33 25 D4 Digital ground supply
DVCC 32 20 34 26 E4 Digital power supply
P2.7 33 N/A 35 N/A N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE)
P2.3/TA0.0/UCA1STE/ A6/CD10 34 N/A 36 27 N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options RGE, YQD)
TA0 CCR0 capture: CCI0B input, compare: Out0 (not available on package options RGE, YQD)
Slave transmit enable – eUSCI_A1 SPI mode (not available on devices without eUSCI_A1)
Analog input A6 – ADC (not available on devices without ADC)
Comparator_D input CD10 (not available on package options RGE, YQD)
P2.4/TA1.0/UCA1CLK/ A7/CD11 35 N/A 37 28 N/A I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options RGE, YQD)
TA1 CCR0 capture: CCI0B input, compare: Out0 (not available on package options RGE, YQD)
Clock signal input – eUSCI_A1 SPI slave mode, Clock signal output – eUSCI_A1 SPI master mode (not available on devices without eUSCI_A1)
Analog input A7 – ADC (not available on devices without ADC)
Comparator_D input CD11 (not available on package options RGE, YQD)
AVSS 36 N/A 38 N/A N/A Analog ground supply
PJ.4/XIN 37 21 1 1 E3 I/O General-purpose digital I/O
Input terminal for crystal oscillator XT1
PJ.5/XOUT 38 22 2 2 E2 I/O General-purpose digital I/O
Output terminal of crystal oscillator XT1
AVSS 39 23 3 3 D3 Analog ground supply
AVCC 40 24 4 4 D2 Analog power supply
QFN Pad Pad Pad N/A N/A N/A QFN package pad. Connection to VSS recommended.
(1) I = input, O = output, N/A = not available
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE.
(3) See Section 6.6 and Section 6.7 for use with BSL and JTAG functions.
(4) See Section 6.7 for use with JTAG function.