SLASE32 Data sheet

SLASE32C August 2014 – August 2018 MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

PM|64
- MTQF008B
RGC|64
- MPQF125F

Thermal pad, mechanical data (Package|Pins)

RGC|64
- QFND102O

Orderable Information

6.3.1 Peripherals in Low-Power Modes

Peripherals can be in different states that impact the achievable power modes of the device. The states depend on the operational modes of the peripherals (see Table 6-2). The states are:

A peripheral is in a high-frequency state if it requires or uses a clock with a "high" frequency of more than 50 kHz.
A peripheral is in a low-frequency state if it requires or uses a clock with a "low" frequency of 50 kHz or less.
A peripheral is in an unclocked state if it does not require or use an internal clock.

If the CPU requests a power mode that does not support the current state of all active peripherals, the device does not enter the requested power mode and instead enters a power mode that still supports the current state of the peripherals, unless an external clock is used. If an external clock is used, the application must ensure that the correct frequency range for the requested power mode is selected.

Table 6-2 Peripheral States

PERIPHERAL	IN HIGH-FREQUENCY STATE⁽¹⁾	IN LOW-FREQUENCY STATE⁽²⁾	IN UNCLOCKED STATE⁽³⁾
WDT	Clocked by SMCLK	Clocked by ACLK	Not applicable
DMA⁽⁴⁾	Not applicable	Not applicable	Waiting for a trigger
RTC_C	Not applicable	Clocked by LFXT	Not applicable
LCD_C	Not applicable	Clocked by ACLK or VLOCLK	Not applicable
Timer_A, TAx	Clocked by SMCLK or clocked by external clock >50 kHz	Clocked by ACLK or clocked by external clock ≤50 kHz.	Clocked by external clock ≤50 kHz.
Timer_B, TBx	Clocked by SMCLK or clocked by external clock >50 kHz	Clocked by ACLK or clocked by external clock ≤50 kHz	Clocked by external clock ≤50 kHz
eUSCI_Ax in UART mode	Clocked by SMCLK	Clocked by ACLK	Waiting for first edge of START bit
eUSCI_Ax in SPI master mode	Clocked by SMCLK	Clocked by ACLK	Not applicable
eUSCI_Ax in SPI slave mode	Clocked by external clock >50 kHz	Clocked by external clock ≤50 kHz	Clocked by external clock ≤50 kHz
eUSCI_Bx in I²C master mode	Clocked by SMCLK or clocked by external clock >50 kHz	Clocked by ACLK or clocked by external clock ≤50 kHz	Not applicable
eUSCI_Bx in I²C slave mode	Clocked by external clock >50 kHz	Clocked by external clock ≤50 kHz	Waiting for START condition or clocked by external clock ≤50 kHz
eUSCI_Bx in SPI master mode	Clocked by SMCLK	Clocked by ACLK	Not applicable
eUSCI_Bx in SPI slave mode	Clocked by external clock >50 kHz	Clocked by external clock ≤50 kHz	Clocked by external clock ≤50 kHz
ESI	Clocked by SMCLK	Clocked by ACLK or ESIOSC	Not applicable
ADC12_B	Clocked by SMCLK or by MODOSC	Clocked by ACLK	Waiting for a trigger
REF_A	Not applicable	Not applicable	Always
COMP_E	Not applicable	Not applicable	Always
CRC⁽⁵⁾	Not applicable	Not applicable	Not applicable
MPY⁽⁵⁾	Not applicable	Not applicable	Not applicable

(1) Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz.

(2) Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.

(3) Peripherals are in a state that does not require or does not use an internal clock.

(4) The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power mode will cause a temporary transition into active mode for the time of the transfer.

(5) Operates only during active mode and will delay the transition into a low-power mode until its operation is completed.