SLASE66C April 2015 – August 2018 MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5922 , MSP430FR59221 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721
PRODUCTION DATA.
The following documents describe the MSP430FR597x(1), MSP430FR592x(1) and MSP430FR587x(1) MCUs. Copies of these documents are available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your device on ti.com (for links to product folders, see Section 8.5). In the upper right corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any revised document.
Errata
Describes the known exceptions to the functional specifications.
Describes the known exceptions to the functional specifications.
Describes the known exceptions to the functional specifications.
Describes the known exceptions to the functional specifications.
Describes the known exceptions to the functional specifications.
Describes the known exceptions to the functional specifications.
Describes the known exceptions to the functional specifications.
Describes the known exceptions to the functional specifications.
User's Guides
Detailed information on the modules and peripherals available in this device family.
The bootloader (BSL) on MSP430 MCUs lets users communicate with embedded memory in the MSP430 MCU during the prototyping phase, final production, and in service. Both the programmable memory (FRAM memory) and the data memory (RAM) can be modified as required.
This document describes the functions that are required to erase, program, and verify the memory module of the MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition, it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the parallel port interface and the USB interface, are described.
Application Reports
This is a getting started guide for obtaining the ULPMark™-CP score using the Embedded Microprocessor Benchmark Consortium (EEMBC) ULPBench™ and EnergyMonitor with the MSP430FR5969 microcontroller (MCU). This document uses the MSP-EXP430FR5969 LaunchPad development kit as the target evaluation module (EVM) for performing the benchmark. ULPBench is a EEMBC benchmark providing an industry-standard method to measure ultra-low-power capabilities of MCUs.
FRAM is a nonvolatile memory technology that behaves like SRAM while enabling a whole host of new applications, but also changes the way firmware should be designed. This application report outlines the how-to and best practices of using FRAM technology in MSP430 from an embedded software development perspective. It discusses how to implement a memory layout according to application-specific code, constant, data space requirements, the use of FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to maximize application robustness by protecting the program code against unintended write accesses.
Selection of the correct crystal, correct load circuit, and proper board layout are important for a stable crystal oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout are given. The document also contains detailed information on the possible oscillator tests to ensure stable oscillator operation in mass production.
System-Level ESD has become increasingly demanding with silicon technology scaling towards lower voltages and the need for designing cost-effective and ultra-low-power components. This application report addresses three different ESD topics to help board designers and OEMs understand and design robust system-level designs.