SLASE66C April   2015  – August 2018 MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5922 , MSP430FR59221 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics - Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM2, LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics, Current Consumption per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.12.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.12.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Wake-up Characteristics
        1. Table 5-9   Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charge
        3. 5.12.4.1    Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.12.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.12.5.1    Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 5-13 Pin-Oscillator Frequency, Ports Px
        5. 5.12.5.2    Typical Characteristics, Pin-Oscillator Frequency
      6. 5.12.6  Timer_A and Timer_B
        1. Table 5-14 Timer_A
        2. Table 5-15 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-16 eUSCI (UART Mode) Clock Frequency
        2. Table 5-17 eUSCI (UART Mode)
        3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-19 eUSCI (SPI Master Mode)
        5. Table 5-20 eUSCI (SPI Slave Mode)
        6. Table 5-21 eUSCI (I2C Mode)
      8. 5.12.8  ADC12
        1. Table 5-22 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-23 12-Bit ADC, Timing Parameters
        3. Table 5-24 12-Bit ADC, Linearity Parameters With External Reference
        4. Table 5-25 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
        5. Table 5-26 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
        6. Table 5-27 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
        7. Table 5-28 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
        8. Table 5-29 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
        9. Table 5-30 12-Bit ADC, Temperature Sensor and Built-In V1/2
        10. Table 5-31 12-Bit ADC, External Reference
      9. 5.12.9  REF Module
        1. Table 5-32 REF, Built-In Reference
      10. 5.12.10 Comparator
        1. Table 5-33 Comparator_E
      11. 5.12.11 FRAM Controller
        1. Table 5-34 FRAM
      12. 5.12.12 Emulation and Debug
        1. Table 5-35 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
      1. 6.3.1 Peripherals in Low-Power Modes
      2. 6.3.2 Idle Currents of Peripherals in LPM3 and LPM4
    4. 6.4  Interrupt Vector Table and Signatures
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  FRAM
    8. 6.8  RAM
    9. 6.9  Tiny RAM
    10. 6.10 Memory Protection Unit (MPU) Including IP Encapsulation
    11. 6.11 Peripherals
      1. 6.11.1  Digital I/O
      2. 6.11.2  Oscillator and Clock System (CS)
      3. 6.11.3  Power-Management Module (PMM)
      4. 6.11.4  Hardware Multiplier
      5. 6.11.5  Real-Time Clock (RTC_C)
      6. 6.11.6  Watchdog Timer (WDT_A)
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  DMA Controller
      9. 6.11.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.11.10 Timer_A TA0, Timer_A TA1
      11. 6.11.11 Timer_A TA2
      12. 6.11.12 Timer_A TA3
      13. 6.11.13 Timer_B TB0
      14. 6.11.14 ADC12_B
      15. 6.11.15 Comparator_E
      16. 6.11.16 CRC16
      17. 6.11.17 CRC32
      18. 6.11.18 AES256 Accelerator
      19. 6.11.19 True Random Seed
      20. 6.11.20 Shared Reference (REF_A)
      21. 6.11.21 Embedded Emulation
        1. 6.11.21.1 Embedded Emulation Module (EEM)
        2. 6.11.21.2 EnergyTrace++ Technology
      22. 6.11.22 Input/Output Diagrams
        1. 6.11.22.1  Digital I/O Functionality Port P1 to P7 and P9
        2. 6.11.22.2  Capacitive Touch Functionality on Port P1 to P7, P9, and PJ
        3. 6.11.22.3  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
        4. 6.11.22.4  Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
        5. 6.11.22.5  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
        6. 6.11.22.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
        7. 6.11.22.7  Port P4 (P4.2 to P4.7) Input/Output With Schmitt Trigger
        8. 6.11.22.8  Port P5 (P5.4 to P5.7) Input/Output With Schmitt Trigger
        9. 6.11.22.9  Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
        10. 6.11.22.10 Port P7 (P7.0 to P7.4) Input/Output With Schmitt Trigger
        11. 6.11.22.11 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
        12. 6.11.22.12 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
        13. 6.11.22.13 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
        14. 6.11.22.14 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Memory
      1. 6.13.1 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-19 eUSCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
tSTE,LEAD STE lead time, STE active to clock UCSTEM = 1, UCMODEx = 01 or 10 1 UCxCLK cycles
tSTE,LAG STE lag time, last clock to STE inactive UCSTEM = 1, UCMODEx = 01 or 10 1
tSTE,ACC STE access time, STE active to SIMO data out UCSTEM = 0, UCMODEx = 01 or 10 2.2 V, 3.0 V 60 ns
tSTE,DIS STE disable time, STE inactive to SOMI high impedance UCSTEM = 0, UCMODEx = 01 or 10 2.2 V, 3.0 V 80 ns
tSU,MI SOMI input data setup time 2.2 V 40 ns
3.0 V 40
tHD,MI SOMI input data hold time 2.2 V 0 ns
3.0 V 0
tVALID,MO SIMO output data valid time(2) UCLK edge to SIMO valid,
CL = 20 pF		 2.2 V 10 ns
3.0 V 10
tHD,MO SIMO output data hold time(3) CL = 20 pF 2.2 V 0 ns
3.0 V 0
(1) fUCxCLK = 1 / 2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-14 and Figure 5-15.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-14 and Figure 5-15.
MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221 MSP430FR5872 MSP430FR58721 MSP430FR5870 eUSCI_master_CKPH0.gifFigure 5-14 SPI Master Mode, CKPH = 0
MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221 MSP430FR5872 MSP430FR58721 MSP430FR5870 eUSCI_master_CKPH1.gifFigure 5-15 SPI Master Mode, CKPH = 1

Table 5-20 lists the characteristics of the eUSCI in SPI slave mode.