SLASE54 Data sheet

SLASE54D March 2016 – January 2021 MSP430FR5962 , MSP430FR5964 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

PM|64
- MTQF008B
ZVW|87
- MPBG401A
PN|80
- MTQF010B
RGZ|48
- MPQF123F

Thermal pad, mechanical data (Package|Pins)

RGZ|48
- QFND031W

Orderable Information

7.2 Pin Attributes

Table 7-1 summarizes the attributes of the pins.

Table 7-1 Pin Attributes

PIN NUMBER ⁽¹⁾				SIGNAL NAME ⁽²⁾ ⁽³⁾	SIGNAL TYPE ⁽⁴⁾	BUFFER TYPE ⁽⁵⁾	POWER SOURCE ⁽⁶⁾	RESET STATE AFTER BOR ⁽⁷⁾
PN	PM	RGZ	ZVW	SIGNAL NAME ⁽²⁾ ⁽³⁾	SIGNAL TYPE ⁽⁴⁾	BUFFER TYPE ⁽⁵⁾	POWER SOURCE ⁽⁶⁾	RESET STATE AFTER BOR ⁽⁷⁾
1	1	1	A10	P1.0	I/O	LVCMOS	DVCC	OFF
				TA0.1	I/O	LVCMOS	DVCC	–
				DMAE0	I	LVCMOS	DVCC	–
				RTCCLK	O	LVCMOS	DVCC	–
				A0	I	Analog	DVCC	–
				C0	I	Analog	DVCC	–
				VREF-	O	Analog	DVCC	–
				VeREF-	I	Analog	DVCC	–
2	2	2	A9	P1.1	I/O	LVCMOS	DVCC	OFF
				TA0.2	I/O	LVCMOS	DVCC	–
				TA1CLK	I	LVCMOS	DVCC	–
				COUT	O	LVCMOS	DVCC	–
				A1	I	Analog	DVCC	–
				C1	I	Analog	DVCC	–
				VREF+	O	Analog	DVCC	–
				VeREF+	I	Analog	DVCC	–
3	3	3	B9	P1.2	I/O	LVCMOS	DVCC	OFF
				TA1.1	I/O	LVCMOS	DVCC	–
				TA0CLK	I	LVCMOS	DVCC	–
				COUT	O	LVCMOS	DVCC	–
				A2	I	Analog	DVCC	–
				C2	I	Analog	DVCC	–
4	4	4	A8	P3.0	I/O	LVCMOS	DVCC	OFF
				A12	I	Analog	DVCC	–
				C12	I	Analog	DVCC	–
5	5	5	B8	P3.1	I/O	LVCMOS	DVCC	–
				A13	I	Analog	DVCC	–
				C13	I	Analog	DVCC	–
6	6	6	B7	P3.2	I/O	LVCMOS	DVCC	OFF
				A14	I	Analog	DVCC	–
				C14	I	Analog	DVCC	–
7	7	7	A7	P3.3	I/O	LVCMOS	DVCC	OFF
				A15	I	Analog	DVCC	–
				C15	I	Analog	DVCC	–
8	–	–	D8	P6.0	I/O	LVCMOS	DVCC	OFF
				UCA3TXD	O	LVCMOS	DVCC	–
				UCA3SIMO	I/O	LVCMOS	DVCC	–
9	–	–	D7	P6.1	I/O	LVCMOS	DVCC	OFF
				UCA3RXD	I	LVCMOS	DVCC	–
				UCA3SOMI	I/O	LVCMOS	DVCC	–
10	–	–	A6	P6.2	I/O	LVCMOS	DVCC	OFF
10	–	–	A6	UCA3CLK	I/O	LVCMOS	DVCC	–
11	–	–	B6	P6.3	I/O	LVCMOS	DVCC	OFF
11	–	–	B6	UCA3STE	I/O	LVCMOS	DVCC	–
12	8	8	D6	P4.7	I/O	LVCMOS	DVCC	OFF
13	9	–	A5	P7.0	I/O	LVCMOS	DVCC	OFF
				UCB2SIMO	I/O	LVCMOS	DVCC	–
				UCB2SDA	I/O	LVCMOS	DVCC	–
14	10	–	B5	P7.1	I/O	LVCMOS	DVCC	OFF
				UCB2SOMI	I/O	LVCMOS	DVCC	–
				UCB2SCL	I/O	LVCMOS	DVCC	–
15	11	–	D5	P8.0	I/O	LVCMOS	DVCC	OFF
16	12	9	A4	P1.3	I/O	LVCMOS	DVCC	OFF
				TA1.2	I/O	LVCMOS	DVCC	–
				UCB0STE	I/O	LVCMOS	DVCC	–
				A3	I	Analog	DVCC	–
				C3	I	Analog	DVCC	–
17	13	10	B3	P1.4	I/O	LVCMOS	DVCC	OFF
				TB0.1	I/O	LVCMOS	DVCC	–
				UCA0STE	I/O	LVCMOS	DVCC	–
				A4	I	Analog	DVCC	–
				C4	I	Analog	DVCC	–
18	14	11	B4	P1.5	I/O	LVCMOS	DVCC	OFF
				TB0.2	I/O	LVCMOS	DVCC	–
				UCA0CLK	I/O	LVCMOS	DVCC	–
				A5	I	Analog	DVCC	–
				C5	I	Analog	DVCC	–
19	15	–	A2	DVSS2	P	Power	–	N/A
20	16	–	A3	DVCC2	P	Power	–	N/A
21	17	12	B1	PJ.0	I/O	LVCMOS	DVCC	OFF
				TDO	O	LVCMOS	DVCC	–
				TB0OUTH	I	LVCMOS	DVCC	–
				SMCLK	O	LVCMOS	DVCC	–
				SRSCG1	O	LVCMOS	DVCC	–
				C6	I	Analog	DVCC	–
22	18	13	C1	PJ.1	I/O	LVCMOS	DVCC	OFF
				TDI	I	LVCMOS	DVCC	–
				TCLK	I	LVCMOS	DVCC	–
				MCLK	O	LVCMOS	DVCC	–
				SRSCG0	O	LVCMOS	DVCC	–
				C7	I	Analog	DVCC	–
23	19	14	C2	PJ.2	I/O	LVCMOS	DVCC	OFF
				TMS	I	LVCMOS	DVCC	–
				ACLK	O	LVCMOS	DVCC	–
				SROSCOFF	O	LVCMOS	DVCC	–
				C8	I	Analog	DVCC	–
24	20	15	D2	PJ.3	I/O	LVCMOS	DVCC	OFF
				TCK	I	LVCMOS	DVCC	–
				SRCPUOFF	O	LVCMOS	DVCC	–
				C9	I	Analog	DVCC	–
25	21	–	D1	P7.2	I/O	LVCMOS	DVCC	OFF
25	21	–	D1	UCB2CLK	I/O	LVCMOS	DVCC	–
26	22	–	D4	P7.3	I/O	LVCMOS	DVCC	OFF
				UCB2STE	I/O	LVCMOS	DVCC	–
				TA4.1	I/O	LVCMOS	DVCC	–
27	23	–	E1	P7.4	I/O	LVCMOS	DVCC	OFF
				TA4.0	I/O	LVCMOS	DVCC	–
				A16	I	Analog	DVCC	–
28	–	–	E2	P7.5	I/O	LVCMOS	DVCC	OFF
28	–	–	E2	A17	I	Analog	DVCC	–
29	–	–	E4	P7.6	I/O	LVCMOS	DVCC	OFF
29	–	–	E4	A18	I	Analog	DVCC	–
30	–	–	F2	P7.7	I/O	LVCMOS	DVCC	OFF
30	–	–	F2	A19	I	Analog	DVCC	–
31	24	16	F1	P4.0	I/O	LVCMOS	DVCC	OFF
31	24	16	F1	A8	I	Analog	DVCC	–
32	25	17	F4	P4.1	I/O	LVCMOS	DVCC	OFF
32	25	17	F4	A9	I	Analog	DVCC	–
33	26	18	G1	P4.2	I/O	LVCMOS	DVCC	OFF
33	26	18	G1	A10	I	Analog	DVCC	–
34	27	19	G2	P4.3	I/O	LVCMOS	DVCC	OFF
34	27	19	G2	A11	I	Analog	DVCC	–
35	28	20	G4	P2.5	I/O	LVCMOS	DVCC	OFF
				TB0.0	I/O	LVCMOS	DVCC	–
				UCA1TXD	O	LVCMOS	DVCC	–
				UCA1SIMO	I/O	LVCMOS	DVCC	–
36	29	21	H1	P2.6	I/O	LVCMOS	DVCC	OFF
				TB0.1	O	LVCMOS	DVCC	–
				UCA1RXD	I	LVCMOS	DVCC	–
				UCA1SOMI	I/O	LVCMOS	DVCC	–
37	30	22	H2	TEST	I	LVCMOS	DVCC	OFF
37	30	22	H2	SBWTCK	I	LVCMOS	DVCC	–
38	31	23	J2	RST	I	LVCMOS	DVCC	OFF
				NMI	I	LVCMOS	DVCC	–
				SBWTDIO	I/O	LVCMOS	DVCC	–
39	–	–	J1	DVSS3	P	Power	–	N/A
40	–	–	K1	DVCC3	P	Power	–	N/A
41	32	24	L2	P2.0	I/O	LVCMOS	DVCC	OFF
				TB0.6	I/O	LVCMOS	DVCC	–
				UCA0TXD	O	LVCMOS	DVCC	–
				BSLTX	O	LVCMOS	DVCC	–
				UCA0SIMO	I/O	LVCMOS	DVCC	–
				TB0CLK	I	LVCMOS	DVCC	–
				ACLK	O	LVCMOS	DVCC	–
42	33	25	L3	P2.1	I/O	LVCMOS	DVCC	OFF
				TB0.0	I/O	LVCMOS	DVCC	–
				UCA0RXD	I	LVCMOS	DVCC	–
				BSLRX	I	LVCMOS	DVCC	–
				UCA0SOMI	I/O	LVCMOS	DVCC	–
43	34	26	K3	P2.2	I/O	LVCMOS	DVCC	OFF
				TB0.2	O	LVCMOS	DVCC	–
				UCB0CLK	I/O	LVCMOS	DVCC	–
44	–	–	L4	P8.1	I/O	LVCMOS	DVCC	OFF
45	–	–	K4	P8.2	I/O	LVCMOS	DVCC	OFF
46	–	–	H4	P8.3	I/O	LVCMOS	DVCC	OFF
47	35	27	K5	P3.4	I/O	LVCMOS	DVCC	OFF
				TB0.3	I/O	LVCMOS	DVCC	–
				SMCLK	O	LVCMOS	DVCC	–
48	36	28	L5	P3.5	I/O	LVCMOS	DVCC	OFF
				TB0.4	I/O	LVCMOS	DVCC	–
				COUT	O	LVCMOS	DVCC	–
49	37	29	H5	P3.6	I/O	LVCMOS	DVCC	OFF
49	37	29	H5	TB0.5	I/O	LVCMOS	DVCC	–
50	38	30	H6	P3.7	I/O	LVCMOS	DVCC	OFF
50	38	30	H6	TB0.6	I/O	LVCMOS	DVCC	–
51	39	31	L6	P1.6	I/O	LVCMOS	DVCC	OFF
				TB0.3	I/O	LVCMOS	DVCC	–
				UCB0SIMO	I/O	LVCMOS	DVCC	–
				UCB0SDA	I/O	LVCMOS	DVCC	–
				BSLSDA	I/O	LVCMOS	DVCC	–
				TA0.0	I/O	LVCMOS	DVCC	–
52	40	32	K6	P1.7	I/O	LVCMOS	DVCC	OFF
				TB0.4	I/O	LVCMOS	DVCC	–
				UCB0SOMI	I/O	LVCMOS	DVCC	–
				UCB0SCL	I/O	LVCMOS	DVCC	–
				BSLSCL	I/O	LVCMOS	DVCC	–
				TA1.0	I/O	LVCMOS	DVCC	–
53	41	–	L7	P5.0	I/O	LVCMOS	DVCC	OFF
				UCB1SIMO	I/O	LVCMOS	DVCC	–
				UCB1SDA	I/O	LVCMOS	DVCC	–
54	42	–	K7	P5.1	I/O	LVCMOS	DVCC	OFF
				UCB1SOMI	I/O	LVCMOS	DVCC	–
				UCB1SCL	I/O	LVCMOS	DVCC	–
55	43	–	K8	P5.2	I/O	LVCMOS	DVCC	OFF
				UCB1CLK	I/O	LVCMOS	DVCC	–
				TA4CLK	I	LVCMOS	DVCC	–
56	44	–	L8	P5.3	I/O	LVCMOS	DVCC	OFF
56	44	–	L8	UCB1STE	I/O	LVCMOS	DVCC	–
57	45	33	H7	P4.4	I/O	LVCMOS	DVCC	OFF
57	45	33	H7	TB0.5	I/O	LVCMOS	DVCC	–
58	46	34	H8	P4.5	I/O	LVCMOS	DVCC	OFF
59	47	35	K9	P4.6	I/O	LVCMOS	DVCC	OFF
60	48	36	L9	DVSS1	P	Power	–	N/A
61	49	37	L10	DVCC1	P	Power	–	N/A
62	50	38	F11	P2.7	I/O	LVCMOS	DVCC	OFF
63	51	39	J11	P2.3	I/O	LVCMOS	DVCC	OFF
				TA0.0	I/O	LVCMOS	DVCC	–
				UCA1STE	I/O	LVCMOS	DVCC	–
				A6	I	Analog	DVCC	–
				C10	I	Analog	DVCC	–
64	52	40	K11	P2.4	I/O	LVCMOS	DVCC	OFF
				TA1.0	I/O	LVCMOS	DVCC	–
				UCA1CLK	I/O	LVCMOS	DVCC	–
				A7	I	Analog	DVCC	–
				C11	I	Analog	DVCC	–
65	53	–	J10	P5.4	I/O	LVCMOS	DVCC	OFF
				UCA2TXD	O	LVCMOS	DVCC	–
				UCA2SIMO	I/O	LVCMOS	DVCC	–
				TB0OUTH	I	LVCMOS	DVCC	–
66	54	–	H10	P5.5	I/O	LVCMOS	DVCC	OFF
				UCA2RXD	I	LVCMOS	DVCC	–
				UCA2SOMI	I/O	LVCMOS	DVCC	–
				ACLK	O	LVCMOS	DVCC	–
67	55	–	G10	P5.6	I/O	LVCMOS	DVCC	OFF
				UCA2CLK	I/O	LVCMOS	DVCC	–
				TA4.0	I/O	LVCMOS	DVCC	–
				SMCLK	O	LVCMOS	DVCC	–
68	56	–	G8	P5.7	I/O	LVCMOS	DVCC	OFF
				UCA2STE	I/O	LVCMOS	DVCC	–
				TA4.1	I/O	LVCMOS	DVCC	–
				MCLK	O	LVCMOS	DVCC	–
69	–	–	F8	P6.4	I/O	LVCMOS	DVCC	OFF
				UCB3SIMO	I/O	LVCMOS	DVCC	–
				UCB3SDA	I/O	LVCMOS	DVCC	–
70	–	–	F10	P6.5	I/O	LVCMOS	DVCC	OFF
				UCB3SOMI	I/O	LVCMOS	DVCC	–
				UCB3SCL	I/O	LVCMOS	DVCC	–
71	–	–	E8	P6.6	I/O	LVCMOS	DVCC	OFF
71	–	–	E8	UCB3CLK	I/O	LVCMOS	DVCC	–
72	–	–	C10	P6.7	I/O	LVCMOS	DVCC	OFF
72	–	–	C10	UCB3STE	I/O	LVCMOS	DVCC	–
73	57	41	E10	AVSS3	P	Power	–	N/A
74	58	42	H11	PJ.6	I/O	LVCMOS	DVCC	–
74	58	42	H11	HFXIN	I	Analog	DVCC	–
75	59	43	G11	PJ.7	I/O	LVCMOS	DVCC	OFF
75	59	43	G11	HFXOUT	O	Analog	DVCC	–
76	60	44	D10	AVSS2	P	Power	–	N/A
77	61	45	E11	PJ.4	I/O	LVCMOS	DVCC	OFF
77	61	45	E11	LFXIN	I	Analog	DVCC	–
78	62	46	D11	PJ.5	I/O	LVCMOS	DVCC	OFF
78	62	46	D11	LFXOUT	O	Analog	DVCC	–
79	63	47	C11	AVSS1	P	Power	–	N/A
80	64	48	B11	AVCC1	P	Power	–	N/A
–	–	–	A1	DGND	P	Power	–	N/A
–	–	–	A11	AGND	P	Power	–	N/A
–	–	–	B10	AGND	P	Power	–	N/A
–	–	–	K2	DGND	P	Power	–	N/A
–	–	–	K10	DGND	P	Power	–	N/A
–	–	–	L1	DGND	P	Power	–	N/A
–	–	–	L11	DGND	P	Power	–	N/A
–	–	Pad	–	QFN Pad	P	Power	–	N/A

(1) N/A = not available

(2) The signal that is listed first for each pin is the reset default pin name.

(3) Signal Types: I = Input, O = Output, I/O = Input or Output.

(4) Buffer Types: LVCMOS, Analog, or Power (see Table 7-3 for details)

(5) To determine the pin mux encodings for each pin, see Section 9.13.

(6) The power source shown in this table is the I/O power source, which may differ from the module power source.

(7) Reset States:
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
N/A = Not applicable