SLASE54 Data sheet

PRODUCTION DATA

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8-18)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_eUSCI	eUSCI input clock frequency	Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10%				16	MHz
f_SCL	SCL clock frequency		2.2 V, 3.0 V	0		400	kHz
t_HD,STA	Hold time (repeated) START	f_SCL = 100 kHz	2.2 V, 3.0 V	4.0			µs
t_HD,STA	Hold time (repeated) START	f_SCL > 100 kHz	2.2 V, 3.0 V	0.6			µs
t_SU,STA	Setup time for a repeated START	f_SCL = 100 kHz	2.2 V, 3.0 V	4.7			µs
t_SU,STA	Setup time for a repeated START	f_SCL > 100 kHz	2.2 V, 3.0 V	0.6			µs
t_HD,DAT	Data hold time		2.2 V, 3.0 V	0			ns
t_SU,DAT	Data setup time		2.2 V, 3.0 V	100			ns
t_SU,STO	Setup time for STOP	f_SCL = 100 kHz	2.2 V, 3.0 V	4.0			µs
t_SU,STO	Setup time for STOP	f_SCL > 100 kHz	2.2 V, 3.0 V	0.6			µs
t_SP	Pulse duration of spikes suppressed by input filter	UCGLITx = 0	2.2 V, 3.0 V	50		250	ns
		UCGLITx = 1		25		125
		UCGLITx = 2		12.5		62.5
		UCGLITx = 3		6.3		31.5
t_TIMEOUT	Clock low time-out	UCCLTOx = 1	2.2 V, 3.0 V		27		ms
		UCCLTOx = 2			30
		UCCLTOx = 3			33

Figure 8-18 I²C Mode Timing