SLASEK0A December   2017  – March 2018 MSP430FR5969-SP

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Signal Descriptions
      1.      Signal Descriptions
    3. 3.3 Pin Multiplexing
    4. 3.4 Connection of Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 4.5  Typical Characteristics – Active Mode Supply Currents
    6. 4.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 4.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 4.8  Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current
    9. 4.9  Typical Characteristics, Current Consumption per Module
    10. 4.10 Thermal Resistance Characteristics
    11. 4.11 Timing and Switching Characteristics
      1. 4.11.1  Power Supply Sequencing
        1. Table 4-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 4-2 SVS
      2. 4.11.2  Reset Timing
        1. Table 4-3 Reset Input
      3. 4.11.3  Clock Specifications
        1. Table 4-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 4-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 4-6 DCO
        4. Table 4-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 4-8 Module Oscillator (MODOSC)
      4. 4.11.4  Wake-up Characteristics
        1. Table 4-9   Wake-up Times From Low-Power Modes and Reset
        2. Table 4-10 Typical Wake-up Charge
        3. 4.11.4.1    Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 4.11.5  Digital I/Os
        1. Table 4-11 Digital Inputs
        2. Table 4-12 Digital Outputs
        3. 4.11.5.1    Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 4-13 Pin-Oscillator Frequency, Ports Px
        5. 4.11.5.2    Typical Characteristics, Pin-Oscillator Frequency
      6. 4.11.6  Timer_A and Timer_B
        1. Table 4-14 Timer_A
        2. Table 4-15 Timer_B
      7. 4.11.7  eUSCI
        1. Table 4-16 eUSCI (UART Mode) Clock Frequency
        2. Table 4-17 eUSCI (UART Mode)
        3. Table 4-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 4-19 eUSCI (SPI Master Mode)
        5. Table 4-20 eUSCI (SPI Slave Mode)
        6. Table 4-21 eUSCI (I2C Mode)
      8. 4.11.8  ADC
        1. Table 4-22 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 4-23 12-Bit ADC, Timing Parameters
        3. Table 4-24 12-Bit ADC, Linearity Parameters With External Reference
        4. Table 4-25 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
        5. Table 4-26 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
        6. Table 4-27 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
        7. Table 4-28 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
        8. Table 4-29 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
        9. Table 4-30 12-Bit ADC, Temperature Sensor and Built-In V1/2
        10. Table 4-31 12-Bit ADC, External Reference
      9. 4.11.9  Reference
        1. Table 4-32 REF, Built-In Reference
      10. 4.11.10 Comparator
        1. Table 4-33 Comparator_E
      11. 4.11.11 FRAM
        1. Table 4-34 FRAM
    12. 4.12 Emulation and Debug
      1. Table 4-35 JTAG and Spy-Bi-Wire Interface
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  CPU
    3. 5.3  Operating Modes
      1. 5.3.1 Peripherals in Low-Power Modes
        1. 5.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
    4. 5.4  Interrupt Vector Table and Signatures
    5. 5.5  Memory Organization
    6. 5.6  Bootloader (BSL)
    7. 5.7  JTAG Operation
      1. 5.7.1 JTAG Standard Interface
      2. 5.7.2 Spy-Bi-Wire Interface
    8. 5.8  FRAM
    9. 5.9  Memory Protection Unit Including IP Encapsulation
    10. 5.10 Peripherals
      1. 5.10.1  Digital I/O
      2. 5.10.2  Oscillator and Clock System (CS)
      3. 5.10.3  Power-Management Module (PMM)
      4. 5.10.4  Hardware Multiplier (MPY)
      5. 5.10.5  Real-Time Clock (RTC_B) (Only MSP430FR596x and MSP430FR594x)
      6. 5.10.6  Watchdog Timer (WDT_A)
      7. 5.10.7  System Module (SYS)
      8. 5.10.8  DMA Controller
      9. 5.10.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 5.10.10 TA0, TA1
      11. 5.10.11 TA2, TA3
      12. 5.10.12 TB0
      13. 5.10.13 ADC12_B
      14. 5.10.14 Comparator_E
      15. 5.10.15 CRC16
      16. 5.10.16 AES256 Accelerator
      17. 5.10.17 True Random Seed
      18. 5.10.18 Shared Reference (REF)
      19. 5.10.19 Embedded Emulation
        1. 5.10.19.1 Embedded Emulation Module (EEM)
        2. 5.10.19.2 EnergyTrace++ Technology
      20. 5.10.20 Peripheral File Map
    11. 5.11 Input and Output Diagrams
      1. 5.11.1  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      2. 5.11.2  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      3. 5.11.3  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      4. 5.11.4  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      5. 5.11.5  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      6. 5.11.6  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      7. 5.11.7  Port P2 (P2.7) Input/Output With Schmitt Trigger
      8. 5.11.8  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      9. 5.11.9  Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
      10. 5.11.10 Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
      11. 5.11.11 Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
      12. 5.11.12 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
      13. 5.11.13 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
      14. 5.11.14 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 5.12 Device Descriptor (TLV)
    13. 5.13 Identification
      1. 5.13.1 Revision Identification
      2. 5.13.2 Device Identification
      3. 5.13.3 JTAG Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Software Best Practices for Radiation Effects Mitigation
    2. 6.2 Device Connection and Layout Fundamentals
      1. 6.2.1 Power Supply Decoupling and Bulk Capacitors
      2. 6.2.2 External Oscillator
      3. 6.2.3 JTAG
      4. 6.2.4 Reset
      5. 6.2.5 Unused Pins
      6. 6.2.6 General Layout Recommendations
      7. 6.2.7 Do's and Don'ts
    3. 6.3 Peripheral- and Interface-Specific Design Information
      1. 6.3.1 ADC12_B Peripheral
        1. 6.3.1.1 Partial Schematic
        2. 6.3.1.2 Design Requirements
        3. 6.3.1.3 Detailed Design Procedure
        4. 6.3.1.4 Layout Guidelines
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Tools and Software
    3. 7.3  Documentation Support
    4. 7.4  Radiation Information
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 4-23 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fADC12CLK Frequency for specified performance For specified performance of ADC12 linearity parameters with ADC12PWRMD = 0.
If ADC12PWRMD = 1, the maximum is 1/4 of the value shown here.		 0.45 5.4 MHz
fADC12CLK Frequency for reduced performance Linearity parameters have reduced performance 32.768 kHz
fADC12OSC Internal oscillator(3) ADC12DIV = 0, fADC12CLK = fADC12OSC from MODCLK 4 4.8 5.4 MHz
tCONVERT Conversion time REFON = 0, Internal oscillator,
fADC12CLK = fADC12OSC from MODCLK, ADC12WINC = 0		 2.6 3.5 µs
External fADC12CLK from ACLK, MCLK, or SMCLK, ADC12SSEL ≠ 0 See (2)
tADC12ON Turnon settling time of the ADC See (1) 100 ns
tADC12OFF Time ADC must be off before it can be turned on again tADC12OFF must be met to make sure that tADC12ON time holds. 100 ns
tSample Sampling time RS = 400 Ω, RI = 4 kΩ,
CI = 15 pF, Cpext= 8 pF(4) 		All pulse sample mode (ADC12SHP = 1) and extended sample mode (ADC12SHP = 0) with buffered reference (ADC12VRSEL = 0x1, 0x3, 0x5, 0x7, 0x9, 0xB, 0xD, 0xF) 1 µs
Extended sample mode (ADC12SHP = 0) with unbuffered reference (ADC12VRSEL= 0x0, 0x2, 0x4, 0x6, 0xC, 0xE) See (5) µs
(1) The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already settled.
(2) 14 × 1 / fADC12CLK. If ADC12WINC = 1, then 15 × 1 / fADC12CLK
(3) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(4) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB: tsample = ln(2n+2) × (RS + RI) × (CI + Cpext), RS< 10 kΩ, where n = ADC resolution = 12, RS= external source resistance, Cpext = external parasitic capacitance.
(5) 6 × 1 / fADC12CLK

Table 4-24 lists the linearity parameters of the ADC when using an external reference.